ISPASS 2009: Boston, Massachusetts, USA

Keynotes

• Joel S. Emer:
  Accelerating architecture research.
  
• Dileep Bhandarkar:
  Performance analysis in the real world of on line services.
  

Real Hardware Measurements

• Wei Huang, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan:
  Differentiating the roles of IR measurement and simulation for power and temperature-aware design. 1-10
  
• Bin Lin, Arindam Mallik, Peter A. Dinda, Gokhan Memik, Robert P. Dick:
  User- and process-driven dynamic voltage and frequency scaling. 11-22
  
• Dmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth:
  Accuracy of performance counter measurements. 23-32
  

Tools

• Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha:
  GARNET: A detailed on-chip network model inside a full-system simulator. 33-42
  
• Julio Merino, Lluc Alvarez, Marisa Gil, Nacho Navarro:
  Cetra: A trace and analysis framework for the evaluation of Cell BE systems. 43-52
  
• Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie:
  Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. 53-64
  

Parallelism

• Milind Kulkarni, Martin Burtscher, Calin Cascaval, Keshav Pingali:
  Lonestar: A suite of parallel irregular programs. 65-76
  
• Venkatesan Packirisamy, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew, Tin-Fook Ngai:
  Exploring speculative parallelism in SPEC2006. 77-88
  
• Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Schulz, Bronis R. de Supinski, Sally A. McKee:
  Machine learning based online performance prediction for runtime parallelization and task scheduling. 89-100
  

Architecture/OS Effects

• Haoqiang Zheng, Jason Nieh:
  WARP: Enabling fast CPU scheduler development and evaluation. 101-112
  
• Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer, Ramesh Illikkal, Donald Newell, Srihari Makineni:
  CMPSched$im: Evaluating OS/CMP interaction on shared cache management. 113-122
  
• Qiming Teng, Peter F. Sweeney, Evelyn Duesterwald:
  Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform. 123-132
  

Workload Characterization and Modeling

• Moriyoshi Ohara, Priya Nagpurkar, Yohei Ueda, Kazuaki Ishizaki:
  The data-centricity of Web 2.0 workloads and its impact on server performance. 133-142
  
• Jeffrey J. Cook, Craig B. Zilles:
  Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. 143-152
  
• Armin Heindl, Gilles Pokam, Ali-Reza Adl-Tabatabai:
  An analytic model of optimistic Software Transactional Memory. 153-162
  

GPU Workloads and Trace Compression

• Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt:
  Analyzing CUDA workloads using a detailed GPU simulator. 163-174
  
• Randy Smith, Neelam Goyal, Justin Ormont, Karthikeyan Sankaralingam, Cristian Estan:
  Evaluating GPUs for network packet signature matching. 175-184
  
• Pierre Michaud:
  Online compression of cache-filtered address traces. 185-194
  

Branch Prediction and Phase Detection

• Nitya Ranganathan, Doug Burger, Stephen W. Keckler:
  Analysis of the TRIPS prototype block predictor. 195-206
  
• Vladimir Uzelac, Aleksandar Milenkovic:
  Experiment flows and microbenchmarks for reverse engineering of branch predictor structures. 207-217
  
• Yu Zhang, Berkin Özisikyilmaz, Gokhan Memik, John Kim, Alok N. Choudhary:
  Analyzing the impact of on-chip network traffic on program phases for CMPs. 218-226
  

Simulation

• Jeff Ringenberg, Trevor N. Mudge:
  SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code. 227-237
  
• Kiyeon Lee, Shayne Evans, Sangyeun Cho:
  Accurately approximating superscalar processor performance from traces. 238-248
  
• Dam Sunwoo, Joonsoo Kim, Derek Chiou:
  QUICK: A flexible full-system functional model. 249-258