Sonoma County, CA, USA Proceedings of the 2001 International Symposium on Physical Design, April 1-4, 2001, Sonoma County, CA, USA. ACM, 2001
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- Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh:
Differences in ASIC, COT and processor design (panel).
- Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances.
- Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
An exact algorithm for coupling-free routing.
- Tao Lin, Lawrence T. Pileggi:
RC(L) interconnect sizing with second order considerations via posynomial programming.
- Yih-Chih Chou, Youn-Long Lin:
A performance-driven standard-cell placer based on a modified force-directed algorithm.
- Patrick H. Madden:
Reporting of standard cell placement results.
- Fook-Luen Heng, Lars Liebmann, Jennifer Lund:
Application of automated design migration to alternating phase shift mask design.
- Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis:
Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs.
- Franklin M. Schellenberg, Luigi Capodieci:
Impact of RET on physical layouts.
- Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun:
Design of robust global power and ground networks.
- Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation for power supply noise suppression.
- Andrew R. Conn, Chandramouli Visweswariah:
Overview of continuous optimization advances and applications to circuit tuning.
- Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava:
Design and analysis of physical design algorithms.
- Phillip Restle, Albert E. Ruehli, Steven G. Walker:
Multi-GHz interconnect effects in microprocessors.
- Wai-Kei Mak:
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.
- Fei Li, Lei He:
Maximum current estimation considering power gating.
- Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng:
Estimating routing congestion using probabilistic analysis.
- Ruiqi Tian, Xiaoping Tang, D. F. Wong:
Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process.
- En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang:
Slicing floorplan design with boundary-constrained modules.
- Sabyasachi Das, Sunil P. Khatri:
A regularity-driven fast gridless detailed router for high frequency datapath designs.
- Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Revisiting floorplan representations.
- Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with super hierarchical constraints.
- Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
ECBL: an extended corner block list with solution space including optimum placement.
- Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie:
Rectilinear block packing using O-tree representation.
- Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh:
Congestion estimation during top-down placement.
- Yangdong Deng, Wojciech Maly:
Interconnect characteristics of 2.5-D system integration scheme.
- Wei-Jin Dai:
Hierarchical physical design methodology for multi-million gate chips.
- Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje:
Overcoming wireload model uncertainty during physical design.
- Zhaoyun Xing, Russell Kao:
A minimum cost path search algorithm through tile obstacles.
- Kolja Sulimma, Wolfgang Kunz:
An exact algorithm for solving difficult detailed routing problems.
- Ankireddy Nalamalpu, Wayne Burleson:
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.
- Rajeev Jayaraman:
Physical design for FPGAs.
- Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar:
A comparative study of two Boolean formulations of FPGA detailed routing constraints.
- Kaustav Banerjee, Massoud Pedram, Amir H. Ajami:
Analysis and optimization of thermal issues in high-performance VLSI.
- Ting-Yuan Wang, Charlie Chung-Ping Chen:
Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method.