Portland, Oregon, USA David Z. Pan, Gi-Joon Nam (Eds.):
Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008.
ACM 2008, ISBN 978-1-60558-048-7
- Antun Domic:
Design or manufacturing: which will be best for the future of the semiconductor roadmap?
Physical optimization techniques with buffering and gate sizing
- David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.
- Jason Cong, John Lee, Lieven Vandenberghe:
Robust gate sizing via mean excess delay minimization.
- Yifang Liu, Jiang Hu, Weiping Shi:
Multi-scenario buffer insertion in multi-core processor designs.
- Bruce Tseng, Hung-Ming Chen:
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.
Advances in placement
- Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-density driven placement for cmp variation and routability.
- Jason Cong, Guojie Luo:
Highly efficient gradient computation for density-constrained analytical placement methods.
- Peter Spindler, Ulf Schlichtmann, Frank M. Johannes:
Abacus: fast legalization of standard cell circuits with minimal movement.
- Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng:
3-D floorplanning using labeled tree and dual sequences.
Statistical and physical design for manufacturability -- act II
Interconnect synthesis and structured ASIC
- Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment.
- M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman:
RF interconnects for communications on-chip.
- Herman Schmit, Amit Gupta, Radu Ciobanu:
Placement challenges for structured ASICs.
Logic optimizations for physical synthesis
Advances in routing
- Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Optimal post-routing redundant via insertion.
- Chih-Hung Liu, Yao-Hsin Chou, Shih-Yi Yuan, Sy-Yen Kuo:
Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree.
- Jieyi Long, Hai Zhou, Seda Ogrenci Memik:
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.
- Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng:
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.
Modern global routing issues and ISPD-08 global routing contest
Electrical issues and clock network design in physical synthesis
- Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto:
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise.
- Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal:
Stress aware layout optimization.
- Rupak Samanta, Jiang Hu, Peng Li:
Discrete buffer and wire sizing for link-based non-tree clock networks.
- Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity and register placement aware gated clock network design.
Physical design for bio-microfluidics
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