ISQED 2004: San Jose, California, USA

ISQED Tutorials: Compact Modeling and Analysis for Nanometer-Scale CMOS Design

• Kerry Bernstein:
  Nanometer-Scale CMOS Devices. 7
  
• Jeff Davis:
  Interconnect Modeling. 7
  
• Andrew B. Kahng:
  Manufacturability . 8
  
• Kaushik Roy:
  Low-Power Design. 8
  
• Nagib Hakim:
  Coping with Uncertainty. 9
  

ISQED Panel Discussion EP1

• Tets Maniwa, Pallab K. Chatterjee:
  Evening Panel Discussion: DFM PDK's: Where Do They Belong To? Are Process Design Kits (PDKs) the Answer for Modern Design for Manufacturing (DFM) Issues? 11-13
  

Plenary Session I

• John Chilton:
  Simplify: Enable Quality, Enable Innovation. 17
  
• Marc E. Levitt:
  Design for Manufacturing? Design for Yield!!! 19
  
• Larry Bock:
  Why Nano Technology? Why Now? And What Might Its Impact on Electronics. 21
  

Physical Design Migration

• Fang Fang, Jianwen Zhu:
  Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. 25-30
  
• Kuang-Kuo Lin, Sudhakar Kale, Aditi Nigam:
  Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design. 31-35
  
• Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera:
  Automatic Generation of Standard Cell Library in VDSM Technologies. 36-41
  

Device and Memory

• Jin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu:
  A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. 45-50
  
• Y. Z. Xu, O. Pohland, C. Cai, Helmut Puchner:
  Leakage Increase of Narrow and Short BCPMOS. 51-54
  
• Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey:
  SRAM Leakage Suppression by Minimizing Standby Supply Voltage. 55-60
  

Poster Session

• Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong:
  Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. 63-68
  
• Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He:
  Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction. 69-74
  
• Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
  Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise. 75-80
  
• Daniela De Venuto:
  New Test Access for High Resolution SD ADC's by Using the Noise Transfer Function Evaluation. 81-85
  
• Stuart McCracken, Zeljko Zilic:
  Design for Testability of FPGA Blocks. 86-91
  
• Nikos Konofaos, G. Ph. Alexiou:
  New Challenges Emerging on the Design of VLSI Circuits Made of MOSFETs Using New Gate Dielectric Materials. 92-97
  
• Dongku Kang, Mark C. Johnson, Kaushik Roy:
  Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. 98-103
  
• Volkan Kursun, Eby G. Friedman:
  Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. 104-109
  
• Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri:
  Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). 110-115
  
• Eren Kursun, Soheil Ghiasi, Majid Sarrafzadeh:
  Transistor Level Budgeting for Power Optimization. 116-121
  
• Sunil Yu, Dusan Petranovic, Shoba Krishnan, Kwyro Lee, Cary Y. Yang:
  Resistance Matrix in Crosstalk Modeling for Muliconductor Systems. 122-125
  
• Bo-Sung Kim, Young-Gi Kim, Soon-Yang Hong:
  Low Power 260 k Color TFT LCD One-Chip Driver IC. 126-130
  
• Woo Hyung Lee, Sanjay Pant, David Blaauw:
  Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. 131-136
  
• Jong-Eun Koo, Kyung-Ho Lee, Young-Hoe Cheon, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong:
  A Variable Reduction Technique for the Analysis of Ultra Large-Scale Power Distribution Networks. 137-142
  
• M. Moiz Khan, Spyros Tragoudas:
  Rewiring for Watermarking Digital Circuits. 143-148
  

ISQED Luncheon Speech

• Michael Keating:
  The IP Quality Revolution. 151-155
  

Topics in Printability

• Michel Côté, Philippe Hurat:
  Layout Printability Optimization Using a Silicon Simulation Methodology. 159-164
  
• Frank Gennari, Andrew R. Neureuther:
  A Pattern Matching System for Linking TCAD and EDA. 165-170
  
• John Ferguson:
  Shifting Methods: Adopting a Design for Manufacture Flow. 171-175
  

Package Design and Interaction

• Lalitha Immaneni, Anju Kapur, Brett Neal:
  Design Tools for Packaging. 179-183
  
• Meigen Shen, Li-Rong Zheng, Hannu Tenhunen:
  Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics. 184-189
  
• Roderick P. Cruz:
  Flip Chip Advanced Package Solder Joint Embrittlement Fault Isolation Using TDR. 190-195
  
• Janet Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar:
  A Clustering Based Area I/O Planning for Flip-Chip Technology. 196-201
  

Test Generation and Application

• Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos:
  Low Power Testing by Test Vector Ordering with Vector Repetition. 205-210
  
• Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy:
  Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. 211-216
  
• Javier Sosa, Juan A. Montiel-Nelson, Héctor Navarro, José C. García:
  Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear Programming. 217-222
  

Modeling and Simulations of Electromigration and Eletromagnetic Effect

• Valeriy Sukharev:
  Physically-Based Simulation of Electromigration Induced Failures in Copper Dual-Damascene Interconnect. 225-231
  
• Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda:
  A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. 232-237
  
• Syed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel:
  Circuit Level Reliability Analysis of Cu Interconnects. 238-243
  
• Pavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway:
  Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. 244-249
  

Interconnect: Capacitance Extraction and Delay Calculation

• Fangqing Yu, Weiping Shi:
  A Divide-and-Conquer Algorithm for 3D Capacitance Extraction. 253-258
  
• Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee:
  A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. 259-264
  
• Y. Quéré, T. LeGouguec, P. M. Martin, F. Huret:
  Interconnect Mode Conversion in High-Speed VLSI Circuits. 265-270
  
• Ye Liu, Mei Xue, Zheng-Fan Li, Rui-Feng Xue:
  Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation. 271-275
  
• Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
  PARADE: PARAmetric Delay Evaluation under Process Variation. 276-280
  

Substrate Noise: Analysis and Prevention

• Ranjit Gharpurey, Edoardo Charbon:
  Substrate Coupling: Modeling, Simulation and Design Perspectives. 283-290
  
• Shahab Ardalan, Manoj Sachdev:
  An Overview of Substrate Noise Reduction Techniques. 291-296
  
• Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai:
  Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs. 297-302
  
• Georgios Veronis, Yi-Chang Lu, Robert W. Dutton:
  Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. 303-308
  
• Henry H. Y. Chan, Zeljko Zilic:
  Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. 309-314
  

ISQED Panel Discussion EP2

• Ron Wilson, Phil Dworsky:
  Evening Panel Discussion: IP Industry: Nordstrom or K-Mart? The Trend Toward Tighter Relationships between Suppliers and Users. 317-319
  

Plenary Session II

• Hiroto Yasuura:
  Digitally Named World: Challenges for New Social Infrastructures. 323
  
• Pierre G. Paulin:
  Designing High Quality, Scaleable SoC??s with Heterogeneous Components. 325
  
• Krishna Saraswat:
  Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics. 327
  

Interconnect Delay and Coupling

• Medha Kulkarni, Tom Chen:
  A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. 331-336
  
• Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim:
  Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on Switching. 337-342
  
• Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
  A Scalable Communication-Centric SoC Interconnect Architecture. 343-348
  

Analysis of Variations

• Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng:
  Application Specific Worst Case Corners Using Response Surfaces and Statistical Models. 351-356
  
• Ting-Yuan Wang, Charlie Chung-Ping Chen:
  SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction. 357-362
  
• Janet Meiling Wang, Omar Hafiz:
  Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method. 363-368
  

Layout and Design Techniques for Quality and Reliability

• Sandeep Koranne:
  A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform. 371-376
  
• Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
  Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. 377-380
  
• Rishi Chaturvedi, Jiang Hu:
  Buffered Clock Tree for High Quality IC Design. 381-386
  

Analog Testing

• Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
  Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. 389-394
  
• Yongquan Fan, Zeljko Zilic, Man Wah Chiang:
  A Versatile High Speed Bit Error Rate Testing Scheme. 395-400
  
• Achintya Halder, Abhijit Chatterjee:
  Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits. 401-406
  

Low Power Design

• Man Lung Mui, Kaustav Banerjee, Amit Mehrotra:
  Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . 409-414
  
• Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
  Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. 415-420
  
• Ge Yang, Zhongda Wang, Sung-Mo Kang:
  Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates. 421-424
  
• Khushwinder Jasrotia, Jianwen Zhu:
  Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. 425-430
  

ESD

• Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo:
  Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. 433-438
  
• Sachio Hayashi, Fumihiro Minami, Masaaki Yamada:
  Full-Chip Analysis Method of ESD Protection Network. 439-444
  
• Ming-Dou Ker, Wen-Yi Chen:
  Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. 445-450
  

DFM Design Techniques

• Justin Gregg, Tom W. Chen:
  Post Silicon Power/Performance Optimization in the Presence of ProcessVariations Using Individual Well Adaptive Body Biasing (IWABB). 453-458
  
• Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris:
  Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction. 459-464
  
• Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala:
  Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. 465-469
  
• Lane Albanese:
  Managing Derivative SoC Design Projects to Better Results. 470-477
  
• Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki:
  IPQ: IP Qualification for Efficient System Design. 478-482
  

Delay Test Issues

• Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
  Delay Fault Diagnosis Using Timing Information. 485-490
  
• Saravanan Padmanaban, Spyros Tragoudas:
  An Adaptive Path Delay Fault Diagnosis Methodology. 491-496
  
• Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
  Scan BIST Targeting Transition Faults Using a Markov Source. 497-502
  
• Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
  The Effect of Threshold Voltages on the Soft Error Rate. 503-508
  

Circuit Design Trends in DSM

• Hari Ananthan, Aditya Bansal, Kaushik Roy:
  FinFET SRAM - Device and Circuit Design Considerations. 511-516
  
• Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman:
  High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. 517-521
  
• Ji Luo, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang, Kuan-Jung Chung, Anthony L. Wilson:
  A High Performance Radiation-Hard Field Programmable Analog Array . 522-527
  
• Ahmad Yazdi, Payam Heydari:
  The Design and Analysis of Non-Uniform Down-Sized Differential Distributed Amplifiers. 528-533
  
• Navid Azizi, Farid N. Najm:
  An Asymmetric SRAM Cell to Lower Gate Leakage. 534-539
  

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