Santa Clara, California, USA Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni (Eds.):
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012.
IEEE 2012, ISBN 978-1-4673-1034-5
Test and Measurement
- Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang:
Physical-design-friendly hierarchical logic built-in self-test - A case study.
- Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee, Duane C. Howard, John D. Cressler:
A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers.
- Tuck-Boon Chan, Andrew B. Kahng:
Improved path clustering for adaptive path-delay testing.
- Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
TSV and DFT cost aware circuit partitioning for 3D-SOCs.
- James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada:
A design-for-test apparatus for measuring on-chip temperature with fine granularity.
Reliable System Design
- Fahad Ahmed, Mohamed M. Sabry, David Atienza, Linda Milor:
Wearout-aware compiler-directed register assignment for embedded systems.
- Davit Mirzoyan, Benny Akesson, Kees Goossens:
Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield.
- Hadi Jahanirad, Karim Mohammadi, Pejman Attarsharghi:
Single fault reliability analysis in FPGA implemented circuits.
- Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty:
Low complexity cross parity codes for multiple and random bit error correction.
- Bao Liu, Xuemei Chen, Fiona Teshome:
Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic.
System Frameworks and Tools
- Shirish Bahirat, Sudeep Pasricha:
A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip.
- Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose:
A preliminary study on system-level impact of persistent main memory.
- Ying Zhang, Lide Duan, Bin Li, Lu Peng:
Optimal microarchitectural design configuration selection for processor hard-error reliability.
- Felipe G. Magalhaes, Oliver B. Longhi, Sergio Johann Filho, Alexandra Aguiar, Fabiano Hessel:
NoC-based platform for embedded software design: An extension of the Hellfire Framework.
Thermal and Power in 3D ICs
- Leslie Hwang, Kevin L. Lin, Martin D. F. Wong:
Thermal via structural design in three-dimensional integrated circuits.
- Sudarshan Srinivasan, Sandip Kundu:
Functional test pattern generation for maximizing temperature in 3D IC chip stack.
- Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method.
- Xuexin Liu, Zao Liu, Sheldon X.-D. Tan, Joseph A. Gordon:
Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method.
- Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong:
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.
- Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi:
A 3D IC designs partitioning algorithm with power consideration.
Low Power Communication Circuits
- Kareem Ragab, Ranjit Gharpurey, Michael Orshansky:
Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation.
- Yongtae Kim, Peng Li:
An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration.
- Karthik Rajagopal:
Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process.
- Sujay Deb, Kevin Chang, Amlan Ganguly, Xinmin Yu, Christof Teuscher, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer:
Design of an efficient NoC architecture using millimeter-wave wireless links.
- Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A novel robust signaling scheme for high-speed low-power communication over long wires.
- Julian Garcia, Ana Rusu:
An extended-range incremental CT ∑Δ ADC with optimized digital filter.
Process-Induced Variability & Hot Spot Detection
- Albert H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, Duane S. Boning:
Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density.
- Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska:
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs.
- Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu:
On lithography aware metal-fill insertion.
- Aaron Gower-Hall, Tamba Gbondo-Tugbawa, JenPin Weng, Wei-tsu Tseng, Laertis Economikos, Toshiaki Yanagisawa, Pavan Bashaboina, Stephen Greco:
Understanding, modeling, and detecting pooling hotspots in copper CMP.
- Li Yu, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, Duane S. Boning:
Methodology for analysis of TSV stress induced transistor variation and circuit performance.
- Rami F. Salem, Mohamed Al-Imam, Abdelrahman ElMously, Haitham Eissa, Ahmed Arafa, Mohab H. Anis:
High performance electrical driven hotspot detection solution for full chip design using a novel device parameter matching technique.
Emerging Topics in EDA
Design & Analysis of Emerging Devices
- Chenyun Pan, Azad Naeemi:
Device- and system-level performance modeling for graphene P-N junction logic.
- Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu:
Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application.
- Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic:
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).
- Shaloo Rakheja, Azad Naeemi:
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits.
- Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas:
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects.
Variation-Aware Design Methodologies
- Vikram B. Suresh, Wayne P. Burleson:
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.
- Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi:
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices.
- Zafar Takhirov, Bobak Nazer, Ajay Joshi:
Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit.
- Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli:
The combined effect of process variations and power supply noise on clock skew and jitter.
- Haiqing Nan, Li Li, Ken Choi:
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.
- Nishant Dhumane, Sandip Kundu:
Critical area driven dummy fill insertion to improve manufacturing yield.
- Roberto Menchaca, Hamid Mahmoodi:
Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS.
- Riadul Islam:
A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.
- Vijaya Kumar Gurugubelli, Shreepad Karmalkar:
A scalable curve-fit model of the substrate coupling resistances for IC design.
- Sachin Shrivastava, Harindranath Parameswaran:
Efficient reduction techniques for statistical model generation of standard cells.
- Huang Kun, Yang Xu, Guoxing Zhao, Zuying Luo:
Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architecture.
- Bin Wu:
Dynamic range estimation for systems with control-flow structures.
- Ali Arabi M. Shahi, Payman Zarkesh-Ha, Mirza Elahi:
Comparison of variations in MOSFET versus CNFET in gigascale integrated systems.
- Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Vertical Slit Field Effect Transistor in ultra-low power applications.
- Tong Xu, Peng Li:
Design and optimization of power gating for DVFS applications.
- Selçuk Köse, Eby G. Friedman, Simon Tarn, Sally Pinzon, Bruce McDermott:
An area efficient on-chip hybrid voltage regulator.
- Patrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin:
Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix.
- Mohammad Abdel-Majeed, Mike Chen, Murali Annavaram:
A case for 3D stacked analog circuits in high-speed sensing systems.
- Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai:
A DyadicCluster method used for nonlinear placement.
- Pinaki Chakrabarti, Vikram Bhatt, Dwight Hill, Aiqun Cao:
Clock mesh framework.
- Ramamurthy Vishweshwara, Nagabhiru Mahita, Ramakrishnan Venkatraman:
Placement aware clock gate cloning and redistribution methodology.
- Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans:
Impact of C-elements in asynchronous circuits.
- Mohit Shah, Brian Mears, Chaitali Chakrabarti, Andreas Spanias:
A top-down design methodology using virtual platforms for concept development.
- Eduardo Antunes, Matheus Soares, Alexandra Aguiar, Sergio Johann Filho, Marcos Sartori, Fabiano Hessel, César A. M. Marcon:
Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC.
- Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization.
- Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake:
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.
- Amith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal:
DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM.
- Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee:
Hierarchical power network synthesis for multiple power domain designs.
- Qiang Ma, Zigang Xiao, Martin D. F. Wong:
Algorithmic study on the routing reliability problem.
Robust SRAM Design
- Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
- G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty:
Process variation tolerant 9T SRAM bitcell design.
- Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi:
History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
- Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey:
VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS.
- Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Bit error rate estimation in SRAM considering temperature fluctuation.
3D Effects on Package Co-Design
- Jonathan Watkins, Jai Pollayil, Calvin Chow, Aveek Sarkar:
Chip-package power delivery network resonance analysis and co-design using time and frequency domain analysis techniques.
- Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee:
Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization.
- Chang Liu, Sung Kyu Lim:
A design tradeoff study with monolithic 3D integration.
- Richard Crisp, Bill Gervasi, Wael Zohni, Bel Haba:
Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMs.
Advanced Analysis & Characterization for Sub-Micron Design
- Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu:
Speed-path analysis for multi-path failed latches with random variation.
- Hironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami:
HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS.
- Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand:
An accurate current source model for CMOS based combinational logic cell.
- Supriyo Maji, Pradip Mandal:
Effcient approaches to overcome non-convexity issues in analog design automation.
- Takeshi Kida, Yasumasa Tsukamoto, Yuji Kihara:
Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis.
- Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah:
Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications.
- Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai:
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.
- Yanzhi Wang, Xue Lin, Younghyun Kim, Naehyuck Chang, Massoud Pedram:
Enhancing efficiency and robustness of a photovoltaic power system under partial shading.
- Atsuki Inoue:
Comparison between power gating and DVFS from the viewpoint of energy efficiency.
- Meeta Srivastav, Michael B. Henry, Leyla Nazhandali:
Design of low-power, scalable-throughput systems at near/sub threshold voltage.
- Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings:
Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms.
- Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura:
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.
Circuit-Level Variability & Manufacturability
- Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai:
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators.
- Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti:
An analytical approach to efficient circuit variability analysis in scaled CMOS design.
- Mustafa Berke Yelten, Paul D. Franzon, Michael B. Steer:
Process mismatch analysis based on reduced-order models.
- Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake:
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.
- Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian:
Theory of redundancy for logic circuits to maximize yield/area.
- Rouwaida Kanj, Rajiv V. Joshi:
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.
Verification & Silicon Debug
Challenges & Opportunities in New Technologies
- Naushad Alam, Bulusu Anand, Sudeb Dasgupta:
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.
- Hsun Li, Meng-Hsueh Chiang:
Design issues and insights of multi-fin bulk silicon FinFETs.
- Xin Huang, Tianwei Zhang, Runsheng Wang, Changze Liu, Yuchao Liu, Ru Huang:
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis.
- Shaloo Rakheja, Vachan Kumar:
Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations.
- Kaiyuan Yang, Dae Hyun Kim, Sung Kyu Lim:
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices.
Energy-Aware System Design
Last update Tue May 21 17:32:30 2013
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- Hao Shen, Jun Lu, Qinru Qiu:
Learning based DVFS for simultaneous temperature, performance and energy management.
- Houman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, Dean M. Tullsen:
Hot peripheral thermal management to mitigate cache temperature variation.
- Kshitij Bhardwaj, Sanghamitra Roy, Koushik Chakraborty:
Power-Performance Yield optimization for MPSoCs using MILP.
- Mahboobeh Ghorbani:
A variation and energy aware ILP formulation for task scheduling in MPSoC.
- Keisuke Inoue, Mineo Kaneko:
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.