ISSS 1998: Hsinchu, Taiwan

Code Generation and Optimization Issues

• Rainer Leupers, Fabian David:
  A Uniform Optimization Technique for Offset Assignment Problems. 3-8
  
• Luc De Coster, Marleen Adé, Rudy Lauwereins, J. A. Peperstraete:
  Code Generation for Compiled Bit-True Simulation of DSP Applications. 9-14
  
• Wei-Kai Cheng, Youn-Long Lin:
  Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. 15-22
  

Invited Talk

• Doris Keitel-Schulz, Norbert Wehn:
  Issues in Embedded DRAM Development and Applications. 23-30
  

IP Reuse and Language

• Chuck Siska:
  A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools. 31-36
  
• Enrica Filippi, Luciano Lavagno, L. Licciardi, A. Montanaro, M. Paolini, Roberto Passerone, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli:
  Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study. 37-42
  
• Frank Vahid, Tony Givargis:
  Incorporating Cores into System-Level Specification. 43-50
  

Poster Presentations

• Rainer Leupers:
  HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. 51-
  
• Apostolos A. Kountouris, Christophe Wolinski:
  False Path Analysis Based on a Hierarchical Control Representation. 55-59
  
• Christoph Jäschke, Rainer Laur:
  Resource Constrained Modulo Scheduling with Global Resource Sharing. 60-65
  
• Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura:
  Statistical Performance-Driven Module Binding in High-Level Synthesis. 66-71
  
• Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto:
  Concurrent Error Detection at Architectural Level. 72-75
  
• Yin-Tsung Hwang, Yuan-Hung Wang:
  Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. 76-82
  

Application-Specific Synthesis Techniques

• Allan Rae, Sri Parameswaran:
  Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. 83-88
  
• Francky Catthoor, Diederik Verkest, Erik Brockmeyer:
  Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications. 89-95
  
• Zhao Wu, Wayne Wolf:
  Data-Path Synthesis of VLIW Video Signal Processors. 96-104
  

Synchronization and Interface Issues

• Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt:
  Synchronization Detection for Multi-Process Hierarchical Synthesis. 105-110
  
• Peter Voigt Knudsen, Jan Madsen:
  Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign. 111-116
  
• Tony Givargis, Frank Vahid:
  Interface Exploration for Reduced Power in Core-Based Systems. 117-124
  

Instruction Encoding and Software Synthesis Techniques

• Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura:
  Instruction Encoding Techniques for Area Minimization of Instruction ROM. 125-130
  
• Ing-Jer Huang, Ping-Huei Xie:
  Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation. 131-136
  
• Wonyong Sung, Junedong Kim, Soonhoi Ha:
  Memory Efficient Software Synthesis from Dataflow Graph. 137-144
  

Partitioning and Scheduling Techniques

• Karam S. Chatha, Ranga Vemuri:
  A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. 145-151
  
• Frank Vahid:
  A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes. 152-157
  
• Soha Hassoun:
  Fine Grain Incremental Rescheduling Via Architectural Retiming. 158-163