ISSS 1999: Boca Raton, Florida, USA

Invited Talks

• Eric M. Foster:
  Design of a Set-Top Box System on a Chip. 2
  
• Brian Kelley:
  On the Rapid Prototyping and Design of a Wireless Communication System on a Chip. 3
  

Embedded Tutorial: Java Compilation Technology

• Brian M. Barry, John Duimovich:
  Embedded Java: Techniques and Applications. 6-7
  

Panel: System-Level Design: Designers' Wish List vs. Reality

• Daniel Gajski, Reinaldo A. Bergamaschi:
  Panel Statement. 8-9
  

Invited Talk

• Nadim Maluf:
  Micro-Electromechanical Systems (MEMS): Miniaturization Beyond Microelectronics. 10-11
  

Embedded Tutorial

• Douglas C. Schmidt:
  Middleware Techniques and Optimizations for Real-Time, Embedded Systems. 12-17
  

Real-Time and Low Power System Design

• Tajana Simunic, Giovanni De Micheli, Luca Benini:
  Event-Driven Power Management of Portable Systems. 18-23
  
• Takanori Okuma, Tohru Ishihara, Hiroto Yasuura:
  Real-Time Task Scheduling for a Variable Voltage Processor. 24-29
  
• Vincent John Mooney III:
  Path-based Edge Activation for Dynamic Run-Time Scheduling. 30-37
  

Performance Issues in System Design

• Jens Horstmannshoff, Heinrich Meyr:
  Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs. 38-43
  
• Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau:
  RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions. 44-50
  
• Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis:
  Pre-Fetching for Improved Core Interfacing. 51-55
  
• Paulo Centoducatte, Ricardo Pannain, Guido Araujo:
  Compressed Code Execution on DSP Architectures. 56-63
  

Memory Design for Embedded Systems

• Fei Chen, Edwin Hsing-Mean Sha:
  Loop Scheduling and Partitions for Hiding Memory Latencies. 64-70
  
• Antoine Fraboulet, Guillaume Huard, Anne Mignotte:
  Loop Alignment for Memory Accesses Optimization. 71-77
  
• Praveen K. Murthy, Shuvra S. Bhattacharyya:
  A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications. 78-84
  
• Chantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Hugo De Man:
  Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications. 85-93
  

Architectural Synthesis

• Khurram Muhammad, Kaushik Roy:
  A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. 94-99
  
• Bart Mesman, Carlos A. Alba Pinto, Koen Van Eijk:
  Efficient Scheduling of DSP Code on Processors with Distributed Register Files. 100-106
  
• Shail Aditya, B. Ramakrishna Rau, Vinod Kathail:
  Automatic Architectural Synthesis of VLIW and EPIC Processors. 107-113
  
• Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz:
  Bit-Width Selection for Data-Path Implementations. 114-121
  

System Design Methodologies

• W. De Rammelaere, K. Eckert, T. Lawell, R. McGarity, F. Steininger, P. Le Moenner, E. Hilkens:
  Catalyst: A DSIP Design Flow Development in Industry. 122-127
  
• Gang Qu, Malena R. Mesarina, Miodrag Potkonjak:
  System Synthesis of Synchronous Multimedia Applications. 128-133
  
• Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
  A Framework for Scheduling and Context Allocation in Reconfigurable Computing. 134-140
  

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