ISVLSI 2005: Tampa, Florida, USA
2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA. IEEE Computer Society 2005 ISBN 0-7695-2365-X
Introduction
- Message from the Technical Program Chair.
- Symposium Committees.
Emerging Trends in VLSI
- Melvin A. Breuer: Let's Think Analog. 2-5
- Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski: Bi-Direction Synthesis for Reversible Circuits. 14-19
Advanced VLSI Design
- Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: Boost Logic: A High Speed Energy Recovery Circuit Family. 22-27
- Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin: High Performance Array Processor for Video Decoding. 28-33
- Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson: Sensing Design Issues in Deep Submicron CMOS SRAMs. 42-45
- Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama: Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. 46-50
VLSI Circuits and Systems
- Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen: 409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. 52-58
- Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler: Two-Phase Resonant Clock Distribution. 65-70
- Huiying Yang, Anuradha Agarwal, Ranga Vemuri: Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. 71-76
- Ana Rusu, Mohammed Ismail, Hannu Tenhunen: A Modified Cascaded Sigma-Delta Modulator with Improved Linearity. 77-82
System-on-a-Chip Design
- Guilin Chen, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir: Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs. 90-95
System Level Design
- Asim Smailagic, Daniel P. Siewiorek, Uwe Maurer, Anthony Rowe, Karen P. Tang: eWatch: Context Sensitive System Design Case Study. 98-103
- Hendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Richard R. Brooks: A Data-Driven Approach for Embedded Security. 104-109
- Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha: System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. 110-116
Field-Programmable and Reconfigurable Systems
- Alexander Thomas, Jürgen Becker: Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. 118-123
- Jong-Ru Guo, Chao You, Michael Chu, Okan Erdogan, Russell P. Kraft, John F. McDonald: A High Speed Reconfigurable Gate Array for Gigahertz Applications. 124-129
- Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula: Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k. 130-135
- Minoru Watanabe, Fuminori Kobayashi: An Improved Dynamic Optically Reconfigurable Gate Array. 136-141
- Tobias Schubert, Bernd Becker: Lemma Exchange in a Microcontroller Based Parallel SAT Solver. 142-147
Application-Specific Low Power VLSI System Design
- Soumik Ghosh, Soujanya Venigalla, Magdy Bayoumi: Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic. 162-166
- Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori: Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. 167-172
- J. H. Han, Ahmet T. Erdogan, Tughrul Arslan: High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization. 173-178
Power Awareness in VLSI Design
- Venkataraman Mahalingam, N. Ranganathan: A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. 180-185
- Daniel Hostetler, Yuan Xie: Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. 186-191
Test and Verification
- Il-soo Lee, Jae-Hoon Jeong, Anthony P. Ambler: Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume. 194-199
- Avijit Dutta, Terence Rodrigues, Nur A. Touba: Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. 200-205
- Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy: Fault Diagnosis and Fault Model Aliasing. 206-211
- Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. 212-217
- Tian Xia, Hao Zheng, Jing Li, Ahmed Ginawi: Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators. 218-223
Physical Design
- Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong: IR Drop and Ground Bounce Awareness Timing Model. 226-231
- Deepak Rautela, Rajendra S. Katti: Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources. 232-237
Poster Papers
- Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li: Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. 248-249
- Renqiu Huang, Ranga Vemuri: Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. 250-251
- Joshua R. Dick, Kenneth B. Kent: Analysis of Incremental Communication for Multilayer Neural Networks on a Field Programmable Gate Array. 252-254
- Il-soo Lee, Yu-Ting Lin, Anthony P. Ambler: Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set. 255-256
- Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Salvatore Pontarelli, Gian-Carlo Cardarilli: Evaluating the Data Integrity of Memory Systems by Configurable Markov Models. 257-259
- Indrajit Atluri, Ashwin K. Kumaraswamy: Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory Usage. 263-265
- Kaiping Zeng, Sorin A. Huss: RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis. 266-267
- Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin: Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. 268-269
- A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil: The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. 270-271
- Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez: Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. 272-273
- Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi: Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. 274-275
- Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model Considering Core Utilization for System on Chip. 276-277
- Young Uk Yim, John F. McDonald, Russell P. Kraft: 12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes. 278-279
- Hau T. Ngo, Rajkiran Gottumukkal, Vijayan K. Asari: A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface. 280-281
- Suryanarayana Tatapudi, José G. Delgado-Frias: A High Performance Hybrid Wave-Pipelined Multiplier. 282-283
- Jurjen Westra, Patrick Groeneveld: Towards Integration of Quadratic Placement and Pin Assignment. 284-286
- Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton: Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. 290-291
- Marco Ottavi, Vamsi Vankamamidi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano: Design of a QCA Memory with Parallel Read/Serial Write. 292-294
- Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar: RG-SRAM: A Low Gate Leakage Memory Design. 295-296
- Adam R. Livingston, Hau T. Ngo, Ming Z. Zhang, Li Tao, Vijayan K. Asari: Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent Approach. 301-302
- Ming Z. Zhang, Hau T. Ngo, Adam R. Livingston, Vijayan K. Asari: An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels. 303-304
- Oswaldo Cadenas, Graham M. Megson, Daniel Jones: A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation. 305-306
- Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jia-Guang Sun: A Hierachical Method for Wiring and Congestion Prediction. 307-308
- Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson: CMOS Realization of Online Testable Reversible Logic Gates. 309-310
- Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert: A Scalable Parallel SoC Architecture for Network Processors. 311-313
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-18T211851 by the dblp team