ISVLSI 2006: Karlsruhe, Germany

Keynotes

• Norbert Wehn:
  Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems. 3
  
• Wayne Wolf:
  Multiprocessor Systems-on-Chips. 4
  

Intellectual Property and Design

• Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin:
  Floorplanning Based on Particle Swarm Optimization. 7-11
  
• Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan:
  Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. 12-17
  
• Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani:
  Adaptive Porting of Analog IPs with Reusable Conservative Properties. 18-23
  
• Wael Adi, Rolf Ernst, Bassel Soudan, Abdulrahman Hanoun:
  VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography. 24-32
  

Physical Design

• Qing K. Zhu, Paige Kolze:
  Metal Fix and Power Network Repair for SOC. 33-37
  
• Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake:
  Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. 38-43
  
• Tan Yan, Shigetoshi Nakatake, Takashi Nojima:
  Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. 44-49
  
• Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy:
  An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors. 50-58
  

High Performance Circuits

• Zhiyu Liu, Volkan Kursun:
  High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages. 59-64
  
• Colm McKillen, Sakir Sezer, Xin Yang:
  High performance service-time-stamp computation for WFQ IP packet scheduling. 65-70
  
• Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui:
  Synthesis of Pipelined SRSL Circuits. 71-76
  
• Romualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner:
  An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard. 77-84
  

Reconfigurable Systems Integration

• Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson:
  Autonomous Realization of Boeing/JPL Sensor Electronics based on Reconfigurable System-on-Chip Technology. 85-90
  
• Rahul Jain, Anindita Mukherjee, Kolin Paul:
  Defect-Aware Design Paradigm for Reconfigurable Architectures. 91-96
  
• Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker:
  New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. 97-102
  
• Victor Aken Ova, Resve Saleh:
  A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. 103-108
  
• Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
  QUKU: A Two-Level Reconfigurable Architecture. 109-116
  

Mixed-Signal Design and Analysis

• Päivi H. Karjalainen, Pekka Heino:
  Space-Saving Layout for Passive Components. 117-121
  
• Supreet Joshi, Dinesh Sharma:
  A Novel Low Power Multilevel Current Mode Interconnect System. 122-127
  
• Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsiang Lo:
  The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel. 128-132
  
• Miguel Figueroa, Esteban Matamala, Gonzalo Carvajal, Seth Bridges:
  Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning. 133-140
  

Test and Verification

• Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade:
  Verification of Scheduling in High-level Synthesis. 141-146
  
• Ming Li, Wen-Ben Jone, Qing-An Zeng:
  An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. 147-152
  
• Xiaoyu Ruan, Rajendra S. Katti:
  An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip. 153-158
  
• Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker:
  Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. 159-166
  

Low Power System Design

• Chan-Hao Chang, Diana Marculescu:
  Design and Analysis of a Low Power VLIW DSP Core. 167-172
  
• Pankaj Golani, Peter A. Beerel:
  High-Performance Noise-Robust Asynchronous Circuits. 173-178
  
• Ilhan Kaya, Taskin Koçak:
  A Low Power Lookup Technique for Multi-Hashing Network Applications. 179-184
  
• J. H. Han, Ahmet T. Erdogan, Tughrul Arslan:
  A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems. 185-192
  

System-on-Chip

• Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi:
  Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. 193-198
  
• Esmail Amini, Mehrdad Najibi, Hossein Pedram:
  Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating. 193-199
  
• Zhonghai Lu, Bei Yin, Axel Jantsch:
  Connection-oriented Multicasting in Wormhole-switched Networks on Chip. 205-2110
  
• Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, Pascal T. Wolkotte:
  A Virtual Channel Network-on-Chip for GT and BE traffic. 211-216
  
• Ethiopia Nigussie, Juha Plosila, Jouni Isoaho:
  Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. 217-224
  

Nano Electronics

• Eric Rachlin, John E. Savage:
  Nanowire Addressing in the Face of Uncertainty. 225-230
  
• Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita:
  Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. 231-236
  
• Jialin Mi, Chunhong Chen:
  Finite State Machine Implementation with Single-Electron Tunneling Technology. 237-241
  
• Xiaobo Sharon Hu, Michael Crocker, Michael T. Niemier, Minjun Yan, Gary H. Bernstein:
  PLAs in Quantum-dot Cellular Automata. 242-250
  

Reconfigurable System Design and Technologies

• Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker:
  Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. 251-256
  
• Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer:
  Regular Routing Architecture for a LUT-based MPGA. 257-262
  
• Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
  A new Multilevel Hierarchical MFPGA and its suitable configuration tools. 263-268
  
• Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon:
  New non-volatile FPGA concept using Magnetic Tunneling Junction. 269-276
  

Complexity and System Organization

• Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke:
  Profile Directed Instruction Cache Tuning for Embedded Systems. 277-282
  
• Yuriy Sheynin, Elena Suvorova, Felix Shutenko:
  Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design. 283-288
  
• Peter Hallschmid, Resve Saleh:
  Fast Configuration of an Energy-Efficient Branch Predictor. 289-294
  
• Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu:
  Exploiting Software Pipelining for Network-on-Chip architectures. 295-302
  

System Level and Circuit Analysis

• Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song:
  An Efficient Algorithm for the Analysis of Cyclic Circuits. 303-308
  
• Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
  Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. 309-316
  

System Level Design

• Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane:
  Optimisation of the SHA-2 Family of Hash Functions on FPGAs. 317-322
  
• Vijay Sundaresan, Ranga Vemuri:
  A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. 323-328
  
• Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate:
  CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. 329-334
  
• Christian Genz, Rolf Drechsler:
  System Exploration of SystemC Designs. 335-342
  

Power Aware VLSI Design

• Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie:
  Reliability-Aware SOC Voltage Islands Partition and Floorplan. 343-348
  
• Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem:
  Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offs. 349-354
  
• Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie:
  Delay and Energy Efficient Data Transmission for On-Chip Buses. 355-360
  
• Jialin Mi, Chunhong Chen:
  Power-Oriented Delay Budgeting for Combinational Circuits. 361-366
  

VLSI Circuits and Optimization

• Alkan Cengiz, Tom W. Chen:
  Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization. 367-372
  
• A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha:
  Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. 373-377
  
• Zhiyi Yu, Bevan M. Baas:
  Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. 378-383
  
• Kiran Puttaswamy, Gabriel H. Loh:
  Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. 384-392
  

VLSI Circuits and Technologies

• Guangyu Chen, Feihui Li, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu:
  Leakage-Aware SPM Management. 393-398
  
• Feng Wang, Yuan Xie, Kerry Bernstein, Yan Luo:
  Dependability Analysis of Nano-scale FinFET circuits. 399-404
  
• Chua-Chin Wang, Gang-Neng Sung:
  A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. 405-410
  

Poster Papers

• Ali Jahanian, Morteza Saheb Zamani:
  Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. 411-415
  
• Seyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam:
  Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption. 416-417
  
• Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar:
  Towards a Faster Simulation of SystemC Designs. 418-419
  
• Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi:
  An Optimized BIST Architecture for FPGA Look-Up Table Testing. 420-421
  
• Suresh Srinivasan, Narayanan Vijaykrishnan:
  Variation Aware Placement for FPGAs. 422-423
  
• Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares:
  A Regular Layout Approach for ASICs. 424-425
  
• José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes:
  Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. 426-427
  
• Johannes Grad, James E. Stine:
  Dual-Mode High-Speed Low-Energy Binary Addition. 428-429
  
• Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel:
  A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. 430-431
  
• Krzysztof Kosciuszkiewicz, Krzysztof Kepa, Fearghal Morgan:
  Transparent Management of Reconfigurable Hardware in Embedded Operating Systems. 432-433
  
• Alisson V. De Brito, Elmar U. K. Melcher, Wilson Rosas:
  An open-source tool for simulation of partially reconfigurable systems using SystemC. 434-435
  
• Florent Berthelot, Fabienne Nouvel:
  Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation. 436-437
  
• David Fang, Filipp Akopyan, Rajit Manohar:
  Self-Timed Thermally-Aware Circuits. 438-439
  
• Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi:
  A New Protocol Stack Model for Network on Chip. 440-441
  
• Jun Zhou, David Kinniment, Gordon Russell, Alexandre Yakovlev:
  A Robust Synchronizer. 442-443
  
• T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J. H. Han:
  Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems. 444-445
  
• Josef Haid, Dietmar Scheiblhofer:
  Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered Systems. 446-447
  
• Hakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir:
  Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems. 448-449
  
• Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran:
  Compiler-Directed Management of Leakage Power in Software-Managed Memories. 450-451
  
• Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin:
  A Parallel Architecture for Hardware Face Detection. 452-453
  
• Ciaran Toal, Sakir Sezer, Xin Yang:
  A VLSI GFP Frame Delineation Circuit. 454-455
  
• Itisha Chanodia, Dimitrios Velenis:
  Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. 456-457