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  IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France. IEEE Computer Society 2008

Keynotes

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  Jürgen Becker: Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. 1-2
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  Christophe Muller: Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories. 3

Design of Arithmetic VLSI Circuits

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  Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez: Arithmetic Data Path Optimization Using Borrow-Save Representation. 4-9
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  Omid Kavehie, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha: Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design. 10-15

Architecture & SoC Design

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  Zhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann: Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. 16-21
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  Deniz Dal, Nazanin Mansouri: Determining the Optimal Number of Islands in Power Islands Synthesis. 22-27

Emerging Technologies

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  Asbjørn Djupdal, Pauline C. Haddow: Defect Tolerance Inspired by Artificial Evolution. 28-33
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  Ismo Hänninen, Jarmo Takala: Reliability of n-Bit Nanotechnology Adder. 34-39
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  Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer: Spintronic Device Based Non-volatile Low Standby Power SRAM. 40-45

Heterogeneous System Design

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  Fahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod: Application of Bottom-Up Methodology to RTW VCO. 46-50
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  Olivier Leman, Laurent Latorre, Frédérick Mailly, Pascal Nouet: A Closed-Loop Architecture with Digital Output for Convective Accelerometers. 51-56
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  Boris Alandry, Norbert Dumas, Laurent Latorre, Frédérick Mailly, Pascal Nouet: A CMOS Multi-sensor System for 3D Orientation Determination. 57-62

Low Power Design I

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  Nainesh Agarwal, Nikitas J. Dimopoulos: FSMD Partitioning for Low Power Using ILP. 63-68
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  Shingo Watanabe, Toshinori Sato: Uncriticality-Directed Low-Power Instruction Scheduling. 69-74
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  Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan D. George: Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices. 75-80
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  Shuai Wang, Jie S. Hu, Sotirios G. Ziavras: BTB Access Filtering: A Low Energy and High Performance Design. 81-86

Multiprocessor SoC

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  Ralf Laue, H. Gregor Molter, Felix Rieder, Sorin A. Huss, Kartik Saxena: A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications. 87-92
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  Issam Maalej, Guy Gogniat, Jean Luc Philippe, Mohamed Abid: System Level Design Space Exploration for Multiprocessor System on Chip. 93-98
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  Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar: A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures. 99-104
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  Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert: MPI-Based Adaptive Task Migration Support on the HS-Scale System. 105-110

Low Power Design II

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  Bahar Jalali Farahani, Anand Meruva: Low Power High Performance Digitally Assisted Pipelined ADC. 111-116
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  Rong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng: A Novel Low-Power Clock Skew Compensation Circuit. 117-121
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  Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet: High Speed Ultra Low Voltage CMOS inverter. 122-127
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  Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas: A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. 128-133

System Level Testing

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  Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang: Process Algebra Based SoC Test Scheduling for Test Time Minimization. 134-138
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  Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre: Improving the Test of NoC-Based SoCs with Help of Compression Schemes. 139-144
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  Michael Higgins, Ciaran MacNamee, Brendan Mullane: A Novel System on Chip (SoC) Test Solution. 145-150
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  Nestor Hernandez, Víctor H. Champac: Testing Skew and Logic Faults in SoC Interconnects. 151-156

High Performance Circuits

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  Qingsheng Hu, Hua-An Zhao, Chen Liu: A Programmable Frequency Divider in 0.18µm CMOS Library. 157-161
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  Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William G. Dunford, Patrick R. Palmer: Energy Recovery from High-Frequency Clocks Using DC-DC Converters. 162-167

Mixed Signal Design

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  Xiao Pu, Axel Thomsen, Jacob Abraham: Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL. 168-172
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  Ahmed El Oualkadi, Denis Flandre: Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. 173-178

Nanoscale Circuits

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  David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat: Impact of Technology Scaling on Digital Subthreshold Circuits. 179-184
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  Behzad Ebrahimi, Saeed Zeinolabedinzadeh, Ali Afzali-Kusha: Low Standby Power and Robust FinFET Based SRAM Design. 185-190
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  Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz: CMOS Control Enabled Single-Type FET NASIC. 191-196

Telecom & Multimedia Architecture Design and Modeling

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  V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi: A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. 197-202
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  Grzegorz Pastuszak: Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection. 203-208
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  Ali Ahmadinia, Balal Ahmad, Tughrul Arslan: Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications. 209-214

Physical Design

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  Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani: Performance Improvement of Physical Retiming with Shortcut Insertion. 215-220
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  Yibo Wang, Yici Cai, Xianlong Hong: A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. 221-226
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  Gustavo Wilke, Ricardo Reis: A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. 227-232
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  Arash Mehdizadeh, Morteza Saheb Zamani, Hosein Shafiei: An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. 233-238

Test & Verification

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  Selina Sha, Bruce Swanson: A Real Case of Significant Scan Test Cost Reduction. 239-244
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  Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan: A Network Based Functional Verification Method of IEEE 1394a PHY Core. 245-250
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  Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan: Cohesive Coverage Management for Simulation and Formal Property Verification. 251-256
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  Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. 257-262

Models for low Power Design

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  Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar: Memory Power Modeling - A Novel Approach. 263-268
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  Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay: Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. 269-274
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  Ali Ahmadinia, Balal Ahmad, Tughrul Arslan: Efficient High-Level Power Estimation for Multi-standard Wireless Systems. 275-280
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  Adnan Kabbani: Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits. 281-285

Dynamic Reconfiguration Management Techniques

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  Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto: Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture. 286-291
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  Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz: SeReCon: A Secure Dynamic Partial Reconfiguration Controller. 292-297
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  Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke: GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. 298-303
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  Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker: Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. 304-309

Hot Topic : Variability-Insensitive Design Techniques

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  Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert: Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. 310-315
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  Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard: Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. 316-321
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  N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Characterisation of FPGA Clock Variability. 322-328
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  Venkataraman Mahalingam, Nagarajan Ranganathan: A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. 329-334

Network On Chip

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  Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen: Flow Maximization for NoC Routing Algorithms. 335-340
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  Everton Carara, Fernando Gehm Moraes: Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip. 341-346
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  Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans: Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. 347-352

VLSI Circuits

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  V. Suresh Babu, Katharine A. A. Rose, M. R. Baiju: Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier. 353-356
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  Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe: A Versatile Linear Insertion Sorter Based on a FIFO Scheme. 357-362

Hot Topic : Temperature-aware Design

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  Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. 363-368
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  Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. 369-374
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  Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres: Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory. 375-380

Reconfigurable-based Circuits & Methods

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  Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin: Standard Cell Like Via-Configurable Logic Block for Structured ASICs. 381-386
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  Andreas Hofmann, Klaus Waldschmidt: SDVM-R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip. 387-392
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  Mohamed B. Abdelhalim, Serag E.-D. Habib: Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme. 393-398
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  Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi: FPGA-Based Circuit Model Emulation of Quantum Algorithms. 399-404

System Level Design & Tools

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  David Andreu, Guillaume Souquet, Thierry Gil: Petri Net Based Rapid Prototyping of Digital Complex System. 405-410
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  Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. 411-416
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  Fabrizio Ferrandi, Pier Luca Lanzi, Daniele Loiacono, Christian Pilato, Donatella Sciuto: A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis. 417-422
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  Hariharan Sankaran, Srinivas Katkoori: Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis. 423-428

Posters 1

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  Padnamabhan Balasubramanian, David A. Edwards: Efficient Realization of Strongly Indicating Function Blocks. 429-432
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  Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol: Virtual Point-to-Point Links in Packet-Switched NoCs. 433-436
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  Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled: Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. 437-440
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  Sunil Shukla, Neil W. Bergmann, Jürgen Becker: A Web Server Based Edge Detector Implementation in FPGA. 441-446
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  Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. 447-450
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  Serge Burckel, Emeric Gioan: In Situ Design of Register Operations. 451-454
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  Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren: An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design. 455-458
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  Rupsa Chakraborty, Dipanwita Roy Chowdhury: Raising the Level of Abstraction for the Timing Verification of System-on-Chips. 459-462
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  Hugo Lebreton, Pascal Vivet: Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. 463-466
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  Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi: Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. 467-470
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  Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani: Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. 471-474

Posters 2

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  Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes: NoC Power Estimation at the RTL Abstraction Level. 475-478
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  Ahmed Jedidi, Badreddine Rejeb, Mohamed Abid: Design of Fractal Image Compression on SOC. 479-482
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  Jin-Hua Hong, Wen-Jie Li: A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier. 483-486
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  Fabien Soulier, Jean-Baptiste Lerat, Lionel Gouyet, Serge Bernard, Guy Cathébras: A Neural Stimulator Output Stage for Dodecapolar Electrodes. 487-490
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  Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner: Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. 491-494
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  Yosi Ben-Asher, Eddie Shochat: Finding the Best Compromise in Compiling Compound Loops to Verilog. 495-498
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  Xun Zhang, Hassan Rabah, Serge Weber: An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip. 499-502
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  Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang: An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. 503-506
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  Mehrdad Najibi, Hossein Pedram: Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading. 507-510
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  Daisaku Seto, Minoru Watanabe: A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. 511-514