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  Proceedings International Test Conference 1982, Philadelphia, PA, USA, November 1982. IEEE Computer Society 1982

Session 1: Invited Speekers

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  Luis T. Burke Jr.: Maintaing Quality, Poductivity and Profit in a Changing Bell System. 4-5
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  Melissa E. Broussard: Higher Yields, Lower Costs. 6-11
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  Matthew V. Mahoney: Closing the Loop: An Expanding Role for ATE in Semiconductor Manufacturing. 12-23

Session 2: Fault Modeling and Test Effectiveness Evaluation for VLSI Circuits

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  Peter S. Bottorff: Fault Modeling and Test Effectiveness Evaluation for VLSI Circuits. 24
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  Yashwant K. Malaiya, Stephen Y. H. Su: A New Fault Model and Testing Technique for CMOS Devices. 25-34
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  C. C. Beh, K. H. Arya, Charles E. Radke, E. Kofi Vida-Torku: Do Stuck Fault Models Reflect Manufacturing Defects? 35-42
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  Alexander Miczo: Fault Modelling for Functional Primitives. 43-51

Session 3: Design for Testability

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  Mark G. Karpovsky: Universal Tests Detecting Input/Output Faults in Almost All Devices. 52-57
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  Erik DeBenedictis, Charles L. Seitz: Testing and Structured Design. 58-62
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  Sumit DasGupta, Prabhakar Goel, Ron G. Walther, Tom W. Williams: A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI. 63-66
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  K. S. Ramanatha, Nripendra N. Biswas: A Design for Complete Testability of Programmable Logic Arrays. 67-74
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  William C. Carter: Signature Testing with Guaranteed Bounds for Fault Coverage. 75-82
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  Prabhakar Goel, M. T. McMahon: Electronic Chip-In-Place Test. 83-91

Session 4: Test Equipment and Methods I

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  Joel M. Schoen: Test Equipment and Methods I. 92
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  William J. Bowhers: Filtering Methods for Fast Ultra-Low Distortion Measurements. 93-104
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  Yasutoshi Otani, Eiji Ishiwa, Nobuo Arai, Yoshio Yamanaka: A Pursuit of Superior Cost-Per-Performance in General-Purpose Linear IC Test System. 105-110
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  David C. Cheng, Alexander A. Grillo: Test Considerations for Components with Redundant Elements. 111-118
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  Kennteth F. Coop: Automated Test Instrumentation for Low-Current Testing. 119-125
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  Bradford Robbins, David K. Oka: Using Analog Signature Analysis in Speech Synthesis Device Testing. 126-131
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  K. S. Bhaskar: Signature Analysis: Yet Another Perspective. 132-139

Panel Session 7: Professional Aspects of Test Engineering

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  John Turino: Professional Aspects of Test Engineering. 140-141
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  Douglas Greenwood: Increasing Test Engineering Effectivness. 142
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  James L. Kroening: Professional Aspects of Test Engineering. 143-145

Session 8: ATPG and Simulation Systems-The State of the Art.

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  Harold Levin: ATPG and Simulation Systems : The State of the Art. 146
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  Kenneth R. Bowden: Design Goals and Implementation Techniques for Time-Based Digital Simulation and Hazard Detection. 147-152
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  David Giles, Charles Berking, Kenneth Wacks: Integrated Functional/Structural Timing for Digital Simulation. 153-160
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  Kyuhik Son, James Y. O. Fong: Automatic Behavioral Test Generation. 161-165
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  John P. Barlow: A New Software Tool for Detecting Problems Caused by Inductively-Generated Switching Noise. 166-169
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  James Y. O. Fong: On Functional Controllability and Observability Analysis. 170-175
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  Charles Hinchcliff: Simplified Microprocessor Test Generation. 176-181

Session 9: Self-Test: Chip Level to System Level Approaches

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  Richard M. Sedmak: Self-Test Chip to System Level Approaches. 182
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  Edward J. McCluskey: Built-In Verification Test. 183-190
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  Thirumalai Sridhar, Satish M. Thatte: Concurrent Checking of Program Flow in VLSI Processors. 191-199
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  Paul H. Bardell, William H. McAnney: Self-Testing of Multichip Logic Modules. 200-204
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  J. Abadir, Yves Deswarte: Run-Time Program for Self-Checking Single Board Computer. 205-213
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  Patrick P. Fasang: A Fault Detection and Isolation Technique for Microcomputers. 214-222

Session 10: Memory-Test-An International Art

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  D. J. Graham: Memory Test : An International Art. 223-224
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  Eugene R. Hnatek, Beau R. Wilson Jr.: An Evaluation of the 2816 EEPROM. 225-235
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  Marian Marinescu: Simple and Efficient Algorithms for Functional RAM Testing. 236-239
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  Y. Hayasaka, K. Shimotori, K. Okada: Testing System for Redundant Memory. 240-244
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  T. Tada, T. Kobayashi, K. Okada, Y. Kuramitsu: Testing of Sense Amplifier in Dynamic Memory. 245-251
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  Nik Kirschner: An Interactive Descrambler Program for RAMs with Redundancy. 252-257
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  Charles E. Shalvoy: Testing during Burn-In: Economical Alternative for Testing Memories. 258-261

Session 11: Quality and Reliability

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  Bill Hedrick: Quality and Reliability. 262
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  Joel P. LeBlanc Jr.: An STL Gate Array Reliability Test Bar. 263-268
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  Louis J. Sobotka: The Effects of Backdriving Digital Integrated Circuits during In-Circuit Testing. 269-286
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  G. Eugene Gottlieb: An Accelerated Testing Technique for Plastic Package Devices Using a Sequential Combination of Pressure Cooker and 85/85 (PCTH). 287-298
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  Willis J. Horth, Frederick G. Hall, Robert G. Hillman: Microelectronic Device Electrical Test Implementation Problems on Automated Test Equipment. 299-307
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  F. G. Cockerill: Quality Control for Production Testing. 308-314
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  Kemon P. Taschioglou: To Measure Quality in the Manufacturing of Printed Circuit Boards. 315-325

Session 12: Test Data Analysis Closes the Production Loop

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  R. Burgess, E. Pignetti, J. Pitti: MCM Data Analysis Tracking System. 326-330
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  Wayne Bryant, Charles Furry, Jim Hahn: Benefits of ATE and Host Computer Networking. 331-338
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  Bruce G. MacAloney, Paul Littlejohn: Manufacturing Productivity: Automated vs. Manual Test-Data-Management Systems. 339-345
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  David W. Malas, Stephen C. Hagan: Test Data Automation: An ATE Distributed Processing Application in a Multi-Vendor Environment. 346-349
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  W. L. Goldie, P. F. Macready: An Automatic Test Equipment Database System Used in the Generation and Analysis of Fault Statistics at the Printed Circuit Board Level. 350-361

Session 13: Testability Measurement and Enhancement

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  William C. Berg, Robert D. Hess: COMET: A Testability Analysis and Design Modification Package. 364-378
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  Eugen I. Muehldorf, Thomas W. Williams: Analysis of the Switching Behavior of Combinatorial Logic Networks. 379-390
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  Vishwani D. Agrawal, M. Ray Mercer: Testability Measures : What Do They Tell Us ? 391-399
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  Ion M. Ratiu, Alberto L. Sangiovanni-Vincentelli, Donald O. Pederson: VICTOR : A Fast VLSI Testability Analysis Program. 397-403

Session 14: Systems Tools

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  Richard A. Albright: System Test. 404
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  John A. Masciola, Mark S. Lucas: A Technique for Testing Large Distributed Systems. 405-408
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  Ken Fedraw: 9826A Computer Burn-In Program. 409-413
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  Donald Komonytsky: LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis. 414-424
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  Kenneth R. Willey: Systems Testing Why ? 425-427

Session 15: Computer Enhanced Analog Test Techniques

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  David C. Cheng: A Precision Measurement Technique for High Frequency Repetitive Signals. 428-434
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  K. Uchida: Testing the Dynamic Performance of High-Speed A/D Converters. 435-440
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  Stephen W. Bryson: Testing an Audio Spectrum Analyzer for Speech Recognition Systems. 441-446
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  Tim Higgins: Digital Signal Processing for Production Testing of Analog LSI Devices. 447-457

Session 16: VLSI/MicroprocessorTests-Making Micrprocessors More Testable

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  Bell Liu: Soft Failure Detection and Correction in Microprocessor Characterization. 458-460
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  Masood Namjoo: Techniques for Concurrent Testing of VLSI Processor Operation. 461-468
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  Vijay S. Iyengar, Larry L. Kinney: Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units. 469-479
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  Sunil Nanda, Sudhakar M. Reddy: Design of Easily Testable Microprocessors : A Case Study. 480-483
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  Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell: An Architecture for Testable VLSI Processors. 484-493

Session 17: Test Software

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  Roger Simpson: Test Software. 494
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  Antony K. Stevens: Structured Programming and the I.C. Test Engineer. 495-4
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  I. M. Watson, John A. Newkirk, Robert G. Mathews, D. B. Boyle: ICTEST : A Unified System for Functional Testing and Simulation of Digital ICs. 499-502
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  Jaques Couesnon, Michel Parot: A Coherent and Efficient Approach to LSI Modeling and Testing for Integrated Circuit Users. 503-508
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  Richard C. Mahoney: A Common Pascal Test Language: Reality or Pipedream. 509-513
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  Iqbal Syed, Nicole Rose: Automated Generation of Device Test Software. 514-521
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  Mike Schell, Mike Sigler: Automated Analysis of Static RAM Failures. 522-527

Session 18: Board Testing I

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  Reymon Oberly: Board Testing. 528
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  Eric H. Millham: Board Test Session I. 529
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  Matthew L. Fichtenbaum: Faults Which Challenge the In-Circuit Tester: Some Examples and Some Solutions. 530-536
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  T. Jackson, P. Vais, K. Schwerbrock: A New Approach to On-Board Microprocessor-Based Self-Test. 537-540
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  Herold Levine, Charles Berking, Alan Blair, Kenneth R. Bowden, Peter deBruyn Kops, David Giles, David Ruhoff, Kenneth Wacks: Design of a New Test Generation System for Performance Testing of LSI Digital Printed Circuit Boards. 541-547
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  Dennis Hebert, Jack H. Arabian: Implications of the Technique for Dynamic High Speed Functional Testing. 548-557

Session 19: Test Economics

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  Gregory Illes: Test System Remote Program Management. 558-564
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  Donald Stewart: Improving the Effectiveness of Board Test Programmers. 565-568
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  William K. Jones: Managing Your Test Cost for the 80's. 569-573
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  G. A. Perone, R. S. Maljatt, J. P. Kain, W. I. Goodheim: A Closer Look at Testing Costs. 574-579

Session 20: VLSI/Microprocessor Tests-New Approaches

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  Ming-Guan Lin, Kenneth Rose: Applying Test Theory to VLSI Testing. 580-586
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  William S. Richardson: Test Pattern Portability for Microprocessors. 587-589
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  Neal H. MacDonald, Gordon B. Neish: An Algorithmic Approach to the Testing of a Wafer Scale Integrated (WSI) Circuit. 590-600
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  Roderick H. Macmillan, M. R. Bentley: , An Efficient Test Vector Generation and Reduction Method for an LSI Digital Filter Circuit Using an Adaptive Search Technique. 601-607

Session 21: Test Equipment and Methods II

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  Richard B. Craven: Test Equipment and Methods II. 608
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  Brian C. Crosby: ECL Board Testing: An In-Circuit Point of View. 609-614
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  Thomas A. Senna: Calculating VOH for LSI 10K ECL. 615-619
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  James Seaton, Jeffrey Axelbank: Designing a High-Speed Vector Bust to Meet the Requirements of Analog LSI Testing. 620-627
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  Junji Nishiura, Toshio Maruyama, Hiromi Maruyama, Shinpei Kamata: Testing VLSI Microprocessor with New Functional Capability. 628-633
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  K. Thangamuthu, M. Macari, S. Cohen: Automated Contactless Digital Test System for VLSI. 634-639

Session 22: Board Testing II

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  R. Oberly: Board Testing II. 640
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  James J. Faran Jr.: Methods of Assignment of Nodes to Pins for Multiplexed Testers. 641-647
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  Hookuong Wong, David Florcik: A Tester-Independent Automated Test Preparation Process for Loaded Boards. 648-655
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  Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte: Analysis and Simulation of Parallel Signature Analyzers. 656-661
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  Peter Solecky, Frank C. Hsu: Board Diagnosis: A Current Assessment and Direction for Future Improvement. 662-670