ITC 1983:
Philadelphia,
PA,
USA
Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983.
IEEE Computer Society 1983 
@proceedings{DBLP:conf/itc/1983,
title = {Proceedings International Test Conference 1983, Philadelphia,
PA, USA, October 1983},
booktitle = {ITC},
publisher = {IEEE Computer Society},
year = {1983},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Keynote Address and Invited Speakers
Session 2:
Test Equipment and Methods-I. VLSI Test System Architecture
- Robert Albrow:
Test Pattern Compaction in VLSI Testers.
12-17
- Steven Ladd:
Implementing a Self-Managed Test Vector Memory with One Million Elements.
18-20
- Y. Kuramitsu, Y. Gamo:
A Suitable Test System for Gate Array.
21-24
- David R. Emberson:
A Tightly Coupled Multiprocessor for VLSI Testing.
25-28
- John R. Schinabeck:
System Architecture for Optimum DC Parameter Measurements.
29-32
- Arthur L. Downey:
Test Program Optimization Techniques for a High Speed Performance VLSI Tester.
33-39
Session 3:
Board Test
Session 4:
Self Test Design Techniques and Evaluation
Session 5:
New Ideas for Test Pattern Generation
Panel Session 6:
The New Generation VLSI Test Sets- 1983 Update
- W. Boggs:
Integration into the CAD Environment.
150
- Steve Bisset:
The Develpment of a Tester-Per-Pin VLSI Test System Architecture.
151-157
Panel Session 7:
Test Technologie in the University
Session 8:
Test Equipment and Methods- VLSI Test System Accuracy and Calibration
Session 9:
Printed Circuit Board Manufacturing Process and Test Data Management
- John C. Howland, Pat T. Harding:
Estimating the Required Size of an Automated Test and Repair System from Subassembly Volume and Failure Information.
212-219
- R. Wade Williams:
Consideration While Introducing a Test Data Management System to the Factory Floor.
220-225
- Jack H. Arabian:
User's Requirements for Automated Handling in Computer Manufacturing and Board Test.
226-237
Session 10:
Intergrated Circuit manufacturing Process and Test Data Management
- Robert W. Atherton, David M. Campbell:
Use of In-Fab Parametric Testing for Process Control of Semiconductor Manufacturing.
238-247
- Donald S. Cleverley:
The Role of Testing in Achieving Zero Defects.
248-253
- Gerry Schmid:
Software Solutions Enhance ATE Networking Capabilities.
254-259
- Alan F. Murray, Peter B. Denyer, David S. Renshaw:
Self-Testing in Bit Serial VLSI Parts: High Coverage at Low Cost.
260-268
- Yacoub M. El-Ziq, Hamid H. Butt:
A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis.
269-274
- Michael A. Schuette, John Paul Shen:
On-Line Self-Monitoring Using Signatured Instruction Streams.
275-282
- Franco Motika, John A. Waicukauski, Edward B. Eichelberger, Eric Lindbloom:
An LSSD Pseudo Random Pattern Test System.
283-288
- W. S. Blackley, M. A. Jack, J. R. Jordan:
A Digital Polarity Correlator Featuring Built-In Self Test and Self Repair Mechanisms.
289-294
- John R. Kuban, Bill Bruce:
The MC6804P2 Built-In Self-Test.
295-301
Session 12:
Computer Aided Test- An International View
Session 13:
"Quo Vadis VLSI Testers or Why Megabucks for Jelly Beans"
Session 14:
Test Economics
Session 15:
Design for Testing in VLSI
Session 16:
Memory Test:
64K and 256K Production Testing
Session 17:
Test Software
Session 18:
Test Equipment and Methods- PC Board Testing
Session 19:
Update on Fault Modeling
Session 20:
Analog and Hybrid Test-1
- Max Khazam:
Predicting Test Accuracy for Analog In-Circuit Testing.
574-577
- Joel Halbert, Mike Koen:
A Waveform Digitizer for Dynamic Testing of High Speed Data Conversion Components.
578-588
- Matthew V. Mahoney:
New Techniques for High Speed Analog Testing.
589-597
- E. A. Sloane, P. W. Dodd:
A General Method for Increasing Converter Accuracy and Resolution.
598-605
- Douglas A. Blakeslee:
Real-Time Automatic Calibration of Analog Test Systems.
606-609
- Phil Carrier:
A Microprocessor Based Method for Testing Transition Noise in Analog to Digital Converters.
610-621
Session 21:
Systems Test
Session 22:
Test Algorithms on the Wall,
Which One is the Best of All?
Session 23:
Design for Testability Tools and Architecture
Session 24:
Memory Test Using Parallel Techniques
Session 25:
Analog and Hybrid Testing- II
Session 26:
Quality and Reliability
Copyright © Sat Nov 21 00:27:31 2009
by Michael Ley (ley@uni-trier.de)
