ITC 1985:
Philadelphia,
PA,
USA
Proceedings International Test Conference 1985, Philadelphia, PA, USA, November 1985.
IEEE Computer Society 1985 
@proceedings{DBLP:conf/itc/1985,
title = {Proceedings International Test Conference 1985, Philadelphia,
PA, USA, November 1985},
booktitle = {ITC},
publisher = {IEEE Computer Society},
year = {1985},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Invited Speekers
Session 1:
Test Economics
Session 2:
Test Generation System Directions - I
- Matthew Adiletta, Elizabeth M. Cooper, Keith Gutfreund:
Automatic Test Generation for Generic Scan Designs.
40-44
- Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller:
Test Generation In Lamp2: System Overview.
45-48
- Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller:
Test Generation In Lamp2: Concepts and Algorithms.
49-56
- Sivanarayana Mallela, Shianling Wu:
A Sequential Circuit Test Generation System.
57-61
- Angelo C. Hung, Francis C. Wang:
A Method for Test Generation Directly from Testability Analysis.
62-78
- Erwin Trischler:
Guided Inconsistent Path Sensitization: Method And Experimental Results.
79-87
Session 3:
Design and Analysis Of Input Stimulus Generation for Built-In-Self Test
Session 4:
Systems Test
Session 5:
Test Equipment:
Calibration and Timing Accuracy
- William Corley, David S. Curry:
RF Calibration in ATE Systems.
180-184
- David C. Chu:
Calibration of Systematic Errors in Precision Time-Interval Counters.
185-190
- Jim Healy, Gary Ure:
A Method of Reducing ATE System Error Components and Guaranteeing Subnanosecond Measurement Accuracies.
191-202
- Dennis Petrich:
Achieving Accurate Timing Measurements on TTL/CMOS Devices in a Manufacturing/Incoming Inspection Environment.
203-219
- Garry C. Gillette:
Timing Accuracy Measurement System.
220-223
Session 6:
Test Technologie in the University
Session 8:
Automatic Test Program Generation Techniques
Session 9:
Test Generation System Directons - II
- Harry H. Chen, Robert G. Mathews, John A. Newkirk:
An Algorithm to Generate Tests for MOS Circuits at the Switch Level.
304-312
- R. Chandramouli, Hector R. Sucar:
Defect Analysis and Fault Modeling in MOS Technology.
313-321
- Mark E. Turner, Duane G. Leet, Ronald J. Prilik, David J. McLean:
Testing CMOS VLSI: Tools, Concepts, and Experimental Results.
322-328
- T. Shimono, K. Oozeki, M. Takahashi, Masato Kawai, S. Funatsu:
An AC/DC Test Generation System for Gate Array LSIs.
329-333
- Kenneth D. Wagner:
The Error Latency of Delay Faults in Combinational and Sequential Circuits.
334-341
- Gordon L. Smith:
Model for Delay Faults Based upon Paths.
342-351
Session 10:
New Developments in Built-In-Self-Test
Session 11:
Non - Traditional Board Testing
- Frans P. M. Beenker:
Systematic and Structured Methods for Digital Board Testing.
380-385
- Stephen F. Filippone:
Automating Test-Bed Fault Detection and Diagnosis.
386-392
- Jaffery C. Phillips:
A Programmable Bus Emulation Technique for Processor Based and Peripheral Printed Circuit Boards.
393-398
- Dom Marro:
Automatic Visual Test of Surface Mount Assemblies.
399-402
- Scott T. Jones:
Flexible Inspection Systems (FIS) for Printed Circuit Board Production: ATE Finds a Quality Partner.
403-412
- Herb Boulton:
New Concepts of Applying Thermographic Testing to Printed Circuit Boards and Finished Products.
413-419
Session 12:
VLSI Test Systems - Solution to Specific Problems
Session 13:
Momory Test - The Changing Scene
- M. Shimizu, N. Okino, J. Nishiura, H. Maruyama:
Memory Embedded VLSI Gate Array Testing.
438-444
- D. Rodgers, M. Shepherd:
Asynchronous FIFO's Require Special Attention.
445-450
- Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano:
Test Pattern Considerations for Fault Tolerant High Density DRAM.
451-455
- T. Fujieda, N. Arai:
Considerations of the Testing of RAMs with Dual Ports.
456-461
- T. Sridhar:
A New Parallel Test Approach for Large Memories.
462-470
- Grady Giles, Craig Hunter:
A Methodology for Testing Content Addressable Memories.
471-475
Session 14:
Test Generation and Design Verification Techniques
Session 15:
Quality/ Reliability
Session 16:
Disign for Testability
Session 17:
The Tester Interface:
Board Testing and Chip Probing
Session 18A:
Tester Interfaces / Debug Tolls
Session 18B:
Test Software Standards
Session 19:
Logic Simulation and Simulation Models
- David Giles, Kenneth R. Bowden, Mike Haney, Gregory A. Maston:
Maintaining Simulation Accuracy through Physical Device Models.
692-695
- Jeremy Richman, Kenneth R. Bowden:
The Modern Fault Dictionary.
696-702
- Ernst Ulrich:
Concurrent Simulation at the Switch, Gate, and Register Levels.
703-709
- William A. Rogers, Jacob A. Abraham:
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
710-716
- Masahiko Kawamura, Kanji Hirabayashi:
AFS : An Approximate Fault Simulator.
717-721
- Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman:
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits.
722-731
Session 20:
Microprocessor / VLSI Test I
Session 21:
Testability Analysis
Session 22:
Advanced Testing Techniques:
Analog Devices and Systems
Session 23:
Artificial Intelligence Applications to Test
Session 24:
Microprocessor / VLSI Test II
Session 25A:
IC Process and Test Data Management
Session 25B:
Printed Circuit Board Manufacturing Process
- Michael Dapron:
Linking Design Tools to In-Circuit Test Systems.
962-971
- Peter Hansen:
Converting Device Test Vectors to an In-Circuit Board Test Environment.
972-979
- Steven R. Nelson:
Distributed Factory Data Management-Breaking the Network Bottleneck.
980-986
Copyright © Thu Nov 26 19:31:42 2009
by Michael Ley (ley@uni-trier.de)
