ITC 1986:
Washington, D.C., USA
Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986.
IEEE Computer Society 1986 
Keynote Speaker
Invited Speakers
Session 1:
Design Techniques for Built-In-Self Test
Session 2:
Using Test Data for Process Improvement
- Dennis Mancl, Mark J. Sullivan:
A Solution to Test Data Acquisition and Management.
60-64
- William W. Bust, Charles R. Darst, Gregory G. Krysl:
ABNER : A Burn-In Monitor and Error Reporting System for PBX Systems Test.
65-73
- Mark D. Winkel:
Using a Relational Database to Develop a Statistical Quality Control System for ATE.
74-79
- Earl Dalton, Walter Ahern, Stephen Denker, Ken Sweitzer, Bill Cooper, Tom Kelly, Stan Smith:
Systematic Yield Improvement in Board Testing Practice.
80-83
- David P. Cohoon, Jey Sheridan:
Case History of Networking a Wafer-Sort Area.
84-89
Session 3:
Test Generation Approaches and Algorithms
- Ioannis Stamelos, M. Melgara, M. Paolini, S. Morpurgo, C. Segre:
A Multi-Level Test Pattern Generation and Validation Environment.
90-96
- Hongtao P. Chang, William A. Rogers, Jacob A. Abraham:
Structured Functional Level Test Generation Using Binary Decision Diagrams.
97-104
- Noriyoshi Itazaki, Kozo Kinoshita:
Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm.
105-112
- Ki Soo Hwang, M. Ray Mercer:
Informed Test Generation Guidance Using Partially Specified Fanout Constraints.
113-120
- Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli:
New Front-End and Line Justification Algorithm for Automatic Test Generation.
121-128
- André Ivanov, Vinod K. Agarwal:
Testability Measures : What Do They Do for ATPG ?
129-139
Session 4:
Meeting the Performance and Complexity Challenge of VLSI
- Gregory Freeman, Dick L. Liu, Bruce A. Wooley, Edward J. McCluskey:
Two CMOS Metastability Sensors.
140-144
- W. C. Bruce, C. C. Hunter, L. A. Basto:
Testing Barrel Shifters in Microprocessors.
145-153
- E. Kofi Vida-Torku, James A. Monzel, Charles E. Radke:
Performance Assurance of Memories Embedded in VLSI Chips.
154-160
- Mark R. Barber, Walter I. Satre:
Timing Measurements on CMOS VLSI Devices Designed to Drive TTL Loads.
161-168
- Jody Van Horn:
Accurate, Cost Effective Performance Screening of VLSI Circuit Designs.
169-175
- George Chiu, Jean-Mark Halbout:
Requirements and Trends for High Speed Testing.
176-181
Session 5:
Trends and Tradeoffs in Test Economics
Session 6:
Poster Session
- Joe Kirschling:
Quickly Developing Effective Codec Tests on an In-Circuit Board Test System.
221-221
- Mark Rich:
A Method of Flexible Catch RAM Display for Memory Testing.
222
- Kemon P. Taschioglou:
Test to Eliminate Test.
223
- Ronald J. Short:
The DASS Needs You ! : An Update on the Activities of the DASS.
224
- Richard Nohelty:
Test System Architecture for Testing Advanced Mixed-Signal Devices.
225-227
Session 7:
Panel Sesion:
Advanced Burn-In and Life Test Techniques
Session 9:
Analysis Techniques for Built-In-Self-Test
- Mark Paraskeva, Anthony P. Ambler, D. F. Burrows, W. L. Knight, I. D. Dear:
Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI.
232-243
- Balakrishnan Krishnamurthy, Ioannis G. Tollis:
Improved Techniques for Estimating Signal Probabilities.
244-251
- Sreejit Chakravarty, Harry B. Hunt III:
On the Computation of Detection Probability for Multiple Faults.
252-262
- Jacob Savir, William H. McAnney:
Random Pattern Testability of Delay Faults.
263-273
- A. J. Briers, K. A. E. Totton:
Random Pattern Testability by Fast Fault Simulation.
274-281
- Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials.
282-289
Session 10:
Advances in Board Test Technology
Session 11:
Modeling, Simulation, and Design Verification
Session 12:
Testing the Newest Generation of Microprocessors
Session 13:
Quality and Reliability
- A. Dale Flowers, Kamlesh Mathur, John Isakson:
Statistical Process Control Using the Parametric Tester.
422-427
- M. Aghazadeh, M. Kirschner:
Transient Thermal Characteristics of VLSI Devices : Evaluation and Application.
428-434
- Mario L. Côrtes, Edward J. McCluskey:
An Experiment on Intermittent-Failure Mechanisms.
435-442
- Jerry M. Soden, Charles F. Hawkins:
Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs.
443-451
- Birger Schneider, Gert Jørgensen, Mogens B. Christensen:
The Effects of Backdrive Stressing Fast IC Technologies.
452-464
- J. Laurent, L. Bergher, Bernard Courtois, Jacques P. Collin:
Towards Automatic Failure Analysis of Complex ICs Through E-Beam Testing.
465-473
Session 14:
Design for Testability-Methods and Measures
Session 15A:
CMOS Modeling, Test Generation, and Fault Simulation
Session 16A:
Inexpensive Testing Techniques
Session 16B:
Advanced Test Approaches and Methods
Session 17:
CAE and Workstation
Session 18:
Advanced Testing of Analog-Digital Devices and Systems
Session 19A:
Design for Testability-PLAs, Scan Paths, and Verification Techniques
Session 19B:
Panel Session:
Deterministic Versus Random Testing
Session 20:
Artificial Intelligence Applications to Test-part I
Session 21:
Accuracy and Performance-They'll Get You Every Time!
Session 22:
Memory Test-From FIFO to Video
- Al Tejeda, George Conner:
Innovative Video RAM Testing.
798-807
- Al Mostacciuolo:
Transmission Problems Encountered When Testing Memory Devices in Parallel on Memory ATE.
808-818
- A. Kanadjian, D. Rodgers, M. Shepherd:
FIFO Test Program Development.
819-825
- Y. Nishimura, M. Hamada, H. Hidaka, H. Ozaki, K. Fujishima, Y. Hayasaka:
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
826-829
- Kim T. Le, Kewal K. Saluja:
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique.
830-839
- T. J. Knips, D. J. Malone:
Designing Characterization Tests for Bipolar Array Performance Verification.
840-847
Session 23:
Software Solutions to Testing Challenges
Session 24:
Systems Test
Session 25:
Artificial Intelligence Applications to Test-Part II
- Bruce L. Havlicsek:
A Knowledge Based Diagnostic System for Automatic Test Equipment.
930-938
- Mary C. Murphy Hoye:
Artificial Intelligence in Semiconductor Manufacturing for Process Development, Functional Diagnostics, and Yield Crash Prevention.
939-946
- Larry Apfelbaum:
Improving In-Circuit Diagnosis of Analog Networks with Expert Systems Techniques.
947-953
- M. Arif Samad, José A. B. Fortes:
Explanation Capabilities in DEFT : A Design-For-Testability Expert System.
954-963
- A. Jesse Wilkinson:
Benchmarking an Expert System for Electronic Diagnosis.
964-971
- Oliver Grillmeyer:
Making a Test System Diagnostic Usable.
972-977
Session 26:
search Techniques That You Can Use!
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