ITC 1998:
Washington,
DC,
USA
Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998.
IEEE Computer Society 1998, ISBN 0-7803-5093-6 
@proceedings{DBLP:conf/itc/1998,
title = {Proceedings IEEE International Test Conference 1998, Washington,
DC, USA, October 18-22, 1998},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-7803-5093-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary
Session 2:
Escaping The High Cost of Test Escapes
Session 3:
Memory Test Algorithms and Pattern Generation
Session 4:
DFT in Practice
Session 5:
Thermal Issues in Manufacturing Test
Session 6:
Embedded Cores
Session 7:
BIST Synthesis
Session 8:
Experimental Results in Current Testing
- Anne E. Gattiker, Wojciech Maly:
Toward understanding "Iddq-only" fails.
174-183
- Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.
184-193
- Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell:
CMOS IC reliability indicators and burn-in economics.
194-203
- Manoj Sachdev, Peter Janssen, Victor Zieren:
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs.
204
Session 9:
MCM Test - Theory and Applications
Session 10:
Mixed-Signal Test Techniques
Session 11:
Integrated Probe Card/Interface Solutions for Specific Test Applications
Session 12:
Access and Test Approaches for Embedded Cores
Session 13:
Test Synthesis
Session 14:
Transistor LeveL Test Techniques
Session 15:
Board and System Test
- Reuben Schrift:
Digital bus faults measuring techniques.
382-387
- John McDermid:
Limited access testing: IEEE 1149.4-instrumentation and methods.
388-395
- Frank W. Angelotti:
Generating interconnect models from prototype hardware.
396-403
Session 16:
Recent Advances in BIST
Session 17:
Introduction to MEMS
Session 18:
Advances in Embedded Core Test
Session 19:
Microprocessor Testing
Session 20:
ATE Architectures:
Cost,
IDDQ and Mixed-Signal Issues
Session 21:
Concurrent Checking
Session 22:
MEMS Fault Modeling and Diagnosis
Session 23:
Test Creation for Implicitly Burning Cores
Session 24:
Revolution and Evolution in Tester Software
- Dan Proskauer:
High quality, easy to use, on time ATE software Can it be done?
597-605
- John Oonk:
Leveraging new standards in ATE software.
606-611
- Craig Force, Tom Austin:
Testing the design: the evolution of test simulation.
612-
Session 25:
Practical ATPG
Session 26:
DFT Theory
Session 27:
Mixed-Signal DFT
Session 29:
Microprocessor Test Tools
- Leland L. Day, Paul A. Ganfield, Dennis M. Rickert, Fred J. Ziegler:
Test methodology for a microprocessor with partial scan.
708-716
- Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott:
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip.
717-726
- Young-Jun Kwon, Ben Mathew, Hong Hao:
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.
727-
Session 30:
Putting thE "Defect" in Defect Diagnosis
- Daniel R. Knebel, Pia Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika:
Diagnosis and characterization of timing-related defects by time-dependent light emission.
733-739
- Mario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee:
Novel optical probing technique for flip chip packaged microprocessors.
740-747
- Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess:
On applying non-classical defect models to automated diagnosis.
748-757
- Yuan-Chieh Hsu, Sandeep K. Gupta:
A new path-oriented effect-cause methodology to diagnose delay failures.
758-
Session 31:
System Level Test Techniques and Processes
Session 32:
The Need for Speed - Timing and Jitter Testing
- Leendert M. Huisman:
Correlations between path delays and the accuracy of performance prediction.
801-808
- Jerry Katz:
High speed testing-have the laws of physics finally caught up with us?
809-813
- Wajih Dalal, Daniel A. Rosenthal:
Measuring jitter of high speed data channels using undersampling techniques.
814-818
- Jan B. Wilstrup:
A method of serial data jitter analysis using one-shot time interval measurements.
819-
Session 33:
Vectors,
Interface,
Probes; ATE Issues in AT-Speed Test
Session 34:
Manufacturing Process Monitoring
- Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill:
A highly testable and diagnosable fabrication process test chip.
853-861
- T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, Joel Ferguson, Jianlin Yu:
Cache RAM inductive fault analysis with fab defect modeling.
862-871
- Ivo Schanstra, Dharmajaya Lukita, A. J. van de Goor, Kees Veelenturf, Paul J. van Wijnen:
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.
872-
Session 35:
Fault Detection and IDDQ
Session 36:
On-Line Testing
Session 37:
Creating Effective Test Sequences
Session 38:
Test Standards - Still Evolving
Session 39:
Design Validation and Diagnosis
Session 40:
Alternatives to IDDQ
Session 41:
BIST Generator and Architectures
Session 42:
New Ideas in Logic Diagnosis
Session 43:
Embedded Memories
- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules.
1102-1111
- Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski:
Built in self repair for embedded high density SRAM.
1112-1119
- Roderick McConnell, Udo Möller, Detlev Richter:
How we test Siemens Embedded DRAM Cores.
1120-
Panel 1:
Good Enough Quality - When is "Enough" Enough
Panel 2:
Two Worlds Collide:
Mixed Signal ASIC Testing
- Keith Baker:
Spice up your life: simulate mixed-signal ICs!
1131
- Mark Burns:
Testing mixed signal SOCs.
1132
- Ken Lanier:
When two worlds merge [test issues for system-level ICs].
1133
Panel 3:
Diagnostic War Stories:
What Saved the Day? A Technique Debate
- Brian Chess:
Accounting for the unexpected: fault diagnosis out of the ivory tower.
1135
- Scott Davidson:
ASIC jeopardy-diagnosing without a FAB.
1136
- Vallluri R. Rao:
Design for diagnostics views and experiences.
1137
- Jayashree Saxena:
IC diagnosis: preventing wars and war stories.
1138
Panel 4:
Scaling Deeper to Submicron:
On-Line Testing to the Rescue
Panel 5:
The Road to System-on-Chip Test - It's a Matter of Cores - Is It?
Panel 6:
BIST vs. ATE:
Which is Better,
for Which IC Tests?
Panel 7:
How Real is the new 1997 SIA Roadmap?
Panel 8:
Academic Research:
Power Plant or Ivory Tower?
- Kwang-Ting Cheng:
National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report.
1157-
Panel 9:
Flying Probers - A New Era in Loaded Board Fixtureless Test
- Jack Ferguson:
Flying probe test systems: capabilities for effective testing.
1163
Panel 10:
Stuck-at Fault:
The Fault Model of Choice for the Third Millennium!?
Best Paper
Copyright © Wed Nov 25 18:58:44 2009
by Michael Ley (ley@uni-trier.de)
