ITC 1999:
Atlantic City,
NJ,
USA
Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999.
IEEE Computer Society 1999 
Session 2: Mcm and Known-Good-Die Testing
Session 3: Dynamic Current Testing
Session 4: Low Power And Diagnosis In Bist
Session 5: Volume Production Testing
Session 6: Microprocessor Testing
Session 7: Board Test - Lecture Series
- Stehpehn F. Scheiber:
Breaking the complexity spiral in board test.
155-158
- Adam W. Ley:
The integration of boundary-scan test methods to a mixed-signal environment.
159-162
- Thomas A. Ziaja:
Using LSSD to test modules at the board level.
163-170
Session 8: Delay Testing
Session 9: Analog Test Methods
Session 10: Virtual And Real Test Software
Session 11: DFT
Session 12: Embedded Memories
Session 13: Mems Fault Modeling and Test
Session 14: Industrial Applications of BIST
- Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada:
Low overhead test point insertion for scan-based BIST.
348-357
- Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski:
Logic BIST for large industrial designs: real issues and case studies.
358-367
- Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
Synthesis of pattern generators based on cellular automata with phase shifters.
368-377
Session 15: Production Wafer Test: Where the Probes Meet the Pads
Session 16: Design Validation and Analysis for Evolving Technologies
Session 17: Board Test: Interconnect Test
Session 18: Enhanced Test and Diagnosis of IC Process Defects
- Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith:
Correlation of logical failures to a suspect process step.
458-476
- Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults.
477-486
Session 19: Embedded Core Test
Session 20: Issues in Tester Accuracy
Session 21: Mixed Signal BIST Techniques
Session 22: Board Test: Practice Makes Perfect
Session 23: Fault Simulation from Bridges to RTL
Session 24: Practicing Embedded Core Test
Session 25: (Panel) Is Analog Fault Simulation a Key to Product Quality? Practical Considerations
- Eugene R. Atwood:
Analog Fault Simulation: Need it? No. It is already done.
649
- Craig Force:
Analog Fault Simulation: Key to Product Quality, or a Foot in the Door.
650
- Hosam Haggag:
Closing The Gap Between Process Development and Mixed Signal Design and Testing.
651
Session 26: On-Line Testing Techniques
Session 27: System Test - Lecture Series
Session 28: Production I - Testing Beyond Single-Threshold Measurements
Session 29:
Testing Analog to Digital Converters
- Turker Kuyel:
Linearity testing issues of analog to digital converters.
747-756
- Nico Csizmadia, Augustus J. E. M. Janssen:
Estimating the integral non-linearity of A/D-converters via the frequency domain.
757-762
- Solomon Max:
Testing high speed high accuracy analog to digital converters embedded in systems on a chip.
763-771
- Turker Kuyel, Haydar Bilhan:
Relating linearity test results to design flaws of pipelined analog to digital converters.
772-779
Session 30:
Issues in High-Speed Testing
Session 31:
Test Methodology State of Practice and Case Studies
Session 32:
System Test Methods from DFT to End of Live
Session 33:
Design for Diagnostics
- Richard H. Livengood, Donna Medeiros:
Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits.
877-882
- William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia Sanda, Steve Wilson, Yuen H. Chan, Antonio Pelella, Stanislav Polonsky:
The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA).
883-891
- Gert-Jan van Rootselaar, Bart Vermeulen:
Silicon debug: scan chains alone are not enough.
892-902
Session 34:
Test Synthesis
Session 35:
Mixed-Signal ATE Issues and Optical Probing
Session 36:
On-Line Testing for FPGAS and Processors
Session 37:
Memory Testing
Session 38:
Test Generation
Session 39:
Advanced Solution for SOC Test
Session 40:
Applying Diagnosis in a Production Test Environment
- David B. Lavo, Tracy Larrabee, Jonathon E. Colburn:
Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis.
1065-1072
- Peilin Song, Franco Motika, Daniel R. Knebel, Rick Rizzolo, Mary P. Kusko, Julie Lee, Moyra K. McManus:
Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor.
1073-1082
- Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
The effects of test compaction on fault diagnosis.
1083-1089
Session 41:
Time-to-Market - Lecture Series
- Jim Johnson:
Is DFT right for you?
1090-1097
- Jon Turino:
Design for test and time to market-friends or foes.
1098-1101
- Bulent Dervisolu:
Design for testability: it is time to deliver it for Time-to-Market.
1102-1111
- Mahesh A. Iyer:
High Time For High Level ATPG.
1112
Panel 1:
High Time for High-Level ATPG
Panel 4:
Thin Gate Oxide Reliability
Panel 6: ITC'99 Benchmark Circuits - Preliminary Results
Panel 7:
Increasing Test Coveratge in VLSI Design
- Jacob A. Abraham:
Position Statement: Increasing Test Coverage in a VLSI Design Course.
1132
- Michael L. Bushnell:
Increasing Test Coverage in a VLSI Design Course.
1133
- John Harrington:
VLSI design 101 - The test module.
1134
- Michel Robert:
Increasing test coverage in a VLSI design course.
1135
- Mani Soma:
Panel Statement: Increasing test coverage in a VLSI design course.
1136
- Wayne Wolf:
Position Statement: Testing in a VLSI Design Course.
1137
- Frans de Jong:
SCITT: Back to Basics in Mass Production Testing.
1138
Panel 8:
SCITT:
Back to Basics in Mass Production Testing
- Frank W. Angelotti:
SCITT: Bringing DRAMs Into the Test Fold.
1139
- Steffen Hellmold:
Static Component Interconnection Test Technology (SCITT).
1140
- David M. Wu:
DFT is all I can afford, who cares about Design for Yield or Design for Reliability!
1141-1142
Panel 9:
DIFT is all I Can Afford,
Who Vares About Design for Yield or Design for Reliability!
Panel 10:
Output in STIL,
Input in STIL
- Nathan Biggs:
STIL: the device-oriented database for the test development lifecycle.
1149
- Brion L. Keller:
Using STIL to describe embedded core test requirements.
1150
- Marc Loranger:
Is there a STIL for mixed signal testing?
1151
ITC'98 Best Paper
Copyright © Tue Nov 17 00:49:51 2009
by Michael Ley (ley@uni-trier.de)
