ITC 2004:
Charlotte,
NC,
USA
Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA.
IEEE 2003, ISBN 0-7803-8581-0 
Cover
- International Test Conference - Cover.
- International Test Conference - Title Page.
- International Test Conference - Copyright.
Introduction
- Welcoming Message.
- Steering Committee and Subcommittees.
- Ned Kornfield Memorial.
- 2003 Paper Awards.
- Technical Program Committee.
- ITC Technical Paper Evaluation and Selection Process.
- 2005 Call for Papers.
- TTTC: Test Technology Technical Council.
- Technical Paper Reviewers.
Session 1:
Plenary
- Bernd Koenemann:
Test In the Era of "What You see Is NOT What You Get".
12
- Robert Madge:
New Test Paradigms for Yield and Manufacturability.
13
Session 2:
Microprocessor Test
- Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono:
AC IO Loopback Design for High Speed µProcessor IO Test.
23-30
- Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
31-37
- David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher:
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor.
38-47
Session 3:
Logic BIST
Session 4:
BIST for Jitter
- Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai:
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems.
77-84
- Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz:
Experimental Results for High-Speed Jitter Measurement Technique.
85-94
- Stephen K. Sunter, Aubin Roy, Jean-Francois Cote:
An Automated, Complete, Structural Test Solution for SERDES.
95-104
Session 5:
Memory Testing
- Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal:
A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis.
105-113
- A. J. van de Goor, Said Hamdioui, Rob Wadsworth:
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.
114-123
- Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli.
124-133
Session 6:
Failure Characterization Methods for IC Diagnosis
- Stas Polonsky, Keith A. Jenkins, Alan J. Weger, Shinho Cho:
CMOS IC diagnostics using the luminescence of OFF-state leakage currents.
134-139
- Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia:
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current.
140-147
- Vijay Reddy, John Carulli, Anand T. Krishnan, William Bosch, Brendan Burgess:
Impact of Negative Bias Temperature Instability on Product Parametric Drift.
148-155
Session 7:
Board and System Test:
At-Speed and Bounce-Free
Session 8:
Methods and Strategies for Optimal Test
- Manu Rehani, David Abercrombie, Robert Madge, Jim Teisher, Jason Saw:
ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test.
181-189
- Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow:
Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions.
190-196
- Peter Patten:
Divide and Conquer based Fast Shmoo algorithms.
197-202
- Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler:
In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost.
203-212
Session 9:
In Search of Small Delay Defects
- Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger:
On Hazard-free Patterns for Fine-delay Fault Testing.
213-222
- Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.
223-231
- Saravanan Padmanaban, Spyros Tragoudas:
A Critical Path Selection Method for Delay Testing.
232-241
- Haihua Yan, Adit D. Singh:
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study.
242-251
Session 10:
Mixed-Signal BIST and DFT
Session 11:
Advances in Testing for Defects
Session 12:
Advances in DFT
Session 13:
Board and System Test:
Board Test Effectiveness
Session 14:
Developments in ATE Software Standards
Session 15:
Handling of Unknowns
- Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher:
X-Tolerant Signature Analysis.
432-441
- Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage.
442-451
- Vivek Chickermane, Brian Foutz, Brion L. Keller:
Channel Masking Synthesis for Efficient On-Chip Test Compression.
452-461
Session 16:
Emerging Technologies Fault Modeling and Tolerance
Session 17:
Advances in Diagnosis
- Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
489-497
- Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski:
Fault Diagnosis in Designs with Convolutional Compactors.
498-507
- Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, V. Rovner, S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.
508-517
Session 18:
Test Economics
- Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane:
An Economic Analysis and ROI Model for Nanometer Test.
518-524
- Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski:
Realizing High Test Quality Goals with Smart Test Resource Usage.
525-533
- Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley:
Low Overhead Delay Testing of ASICS.
534-542
Session 19:
Board and System Test:
Extending Boundary-Scan to RF and HS Serial Testing
Session 20:
Squeezing the Picoseconds
Session 21:
ATPG/FAULT Simulation Specialties
Session 22:
Interconnect Testing and Fault Diagnosis in FPGAS
Session 23:
Industry Case Studies in Testing
Session 24:
Lecture Series - Test Trends and Challenges
Session 25:
Board and System Test:
System and Field Test
Session 26:
ATE for the Fastest Devices
- Mohamed Hafed, Antonio H. Chan, Geoffrey Duerden, Bardia Pishdad, Clarence Tam, Sebastien Laberge, Gordon W. Roberts:
A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing.
728-737
- A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson:
Tester Architecture For The Source Synchronous Bus.
738-747
- David C. Keezer, Dany Minier, F. Binette:
Modular Extension of ATE to 5 Gbps.
748-757
Session 27:
SoC:
Mixed Signals,
Size and Speed
- Hans T. Heineken, Jitendra Khare:
Test Strategies For a 40Gbps Framer SoC.
758-763
- Bernd Laquai:
A Model-based Test Approach for Testing High-Speed PLLs and Phase Regulation Circuitry in SOC Devices.
764-772
- K. Nikila, Rubin A. Parekhji:
DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.
773-782
Session 28:
RF Testing
Session 29:
State Space Exploration and Test Generation
Session 30:
SoC Test Case Studies
Session 31:
Board and System Test:
Board and System-Level BIST Techniques
Session 32:
Test of Digital,
Analog and MEMS C
- Fei Su, Krishnendu Chakrabarty:
Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays.
883-892
- Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski:
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.
893-902
- Ali Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor:
I/O Self-Leakage Test.
903-906
- Sreejit Chakravarty, Eric W. Savage, Eric N. Tran:
Defect Coverage Analysis of Partitioned Testing.
907-915
Session 33:
Test Compression
- Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai:
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
916-925
- Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand:
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.
926-935
- Kedarnath J. Balakrishnan, Nur A. Touba:
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion.
936-944
- Baris Arslan, Alex Orailoglu:
Test Cost Reduction Through A Reconfigurable Scan Architecture.
945-952
Session 34:
Mixed-Signal Test Techniques
Session 35:
Embedded Memories BIST and Repair
- Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi:
Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.
988-996
- Robert C. Aitken:
A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories.
997-1005
- Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez:
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.
1006-1015
- Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii:
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM.
1016-1023
Session 36:
Delay Testing
Session 37:
Application Series - Board and System-Level DFT and Test
Session 38:
Formalizing and Simulating ATE
Session 39:
Testing for Speed - New and Practical Methods
Session 40:
Picosecond Jitter Testing
Session 41:
Application Series - Wafer Probe Technology
Session 42:
Wrappers and More
- Qiang Xu, Nicola Nicolici:
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores.
1196-1202
- Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
1203-1212
- Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization.
1213-1222
Session 43:
Design-for-Availability
Session 44:
Advances in Tester Architecture
Session 45:
Advances in Delay Testing
- Bipul Chandra Paul, Cassondra Neau, Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
1269-1275
- Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi:
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.
1276-1284
- Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski:
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.
1285-1294
Session 46:
Application Series - Jitter in Test
Session 47:
On-Line Testing and Fault Tolerance at Low Cost
Session 48:
Advances in SoC Test
Session 49:
ADC Testing
Panel 1:
Open Architecture ATE:
Reality or Dream?
Panel 2:
Security vs. Test Quality:
Can we only have one at a time?
- Erik Jan Marinissen:
Security vs. Test Quality: Can We Really Only Have One at a Time?
1411
- Hérvé Fleury:
Electronic circuit comprising a secret sub-module.
1412
- Stephen Pateras:
Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.
1413
- Rohit Kapur:
Security vs. Test Quality: Are they mutually exclusive?.
1414
- Laurent Sourgen:
Testing a secure device: High coverage with very low observability.
1415
Panel 3:
Glamorous Analog Testability - We Already Test them and Ship Them... So What is the Problem?
- Mohamed Hafed:
Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem?
1416
Panel 4:
100 DPM in Nanometer Technology - Is it Achievable?
- Greg Aldrich:
100 DPPM in Nanometer Technology - Is it achievable?
1417
- Brady Benware:
Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs.
1418
- Kenneth M. Butler:
Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya.
1419
- Phil Nigh:
Achieving Quality Levels of 100dpm: It's possible - but roll up your sleeves and be prepared to do some work..
1420
- Sanjay Sengupta:
Test Strategies for Nanometer Technologies.
1421
- Thomas M. Storey:
Testing in a high volume DSM Environment.
1422
Panel 5:
What Do You Mean My Board Test Stinks?
Panel 6:
DUDE! Where's My Data? - Cracking Open the Hermetically Sealed Tester
- W. Robert Daasch, Manu Rehani:
Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester.
1428
- Phil Nigh:
Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization".
1429
- Robert Madge:
ATE Value Add through Open Data Collection.
1430
Panel 7:
Cost of Test:
Taking Control
Panel 8:
Is "Design-to-Production" The Ultimate Answer for Jitter,
Noise,
and BER Challenges for Multi-GB/S ICs?
- Mike Li:
Is "Design to Production" The Ultimate Answer For Jitter, Noise, and BER Challenges For Multi GB/s ICs?.
1433
- Takahiro J. Yamaguchi:
Loopback or not?
1434
- John C. Johnson:
Options for High-Volume Test of Multi-GB/s Ports.
1435
- Mike Li:
Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs?
1436
- Jim Sproch:
A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals.
1437
Panel 9:
Diagnosis Meets Physical Failure Analysis:
How Long Can We Succeed?
- Yukio Okuda:
Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?
1438
- Thomas Bartenstein:
Panel 9 - Diagnostics vs. Failure Analysis.
1439
- Edward I. Cole Jr.:
Global Failure Localization: We Have To, But on What and How?.
1440
- Anne E. Gattiker:
Diagnosis Meets Physical Failure Analysis: How Long can we Succeed?
1441
- Srikanth Venkataraman:
Diagnosis meets Physical Failure Analysis: What is needed to succeed?.
1442
- Kiyoshi Nikawa:
How long can we succeed using the OBIRCH and its derivatives ?.
1443
Panel 10:
Investment vs. Yield Relationship for Memories in SoC
- Yervant Zorian:
Investment vs. Yield Relationship for Memories in SOC.
1444
- Jitendra Khare:
Memory Yield Improvement - SoC Design Perspective.
1445
- Joseph A. Reynick:
Investment vs. Yield Relationship for Memories and IP in SOC.
1446
- Jun Qian:
Plan Ahead for Yield.
1447
ITC 2003 Best Paper
Copyright © Wed Nov 25 18:58:45 2009
by Michael Ley (ley@uni-trier.de)
