ITC 2006: Santa Clara, California, USA

• Lee Whetsel:
  A High Speed Reduced Pin Count JTAG Interface. 1-10
  
• Jeff Rearick, Aaron Volz:
  A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. 1-8
  
• Hung-chi Lihn:
  Reusable, Low-cost, and Flexible Multidrop System JTAG Architecture. 1-10
  
• Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato:
  Recognition of Sensitized Longest Paths in Transition Delay Test. 1-6
  
• Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich:
  Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. 1-9
  
• Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore:
  Comparison of Delay Tests on Silicon. 1-10
  
• Franco Stellari, Peilin Song, Tim Diemoz, Alan J. Weger, Tami Vogel, Steve Wilson, John Pennings, Richard F. Rizzolo:
  High-Voltage and High-Power PLL Diagnostics using Advanced Cooling and Emission Images. 1-10
  
• Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
  Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. 1-10
  
• Rao Desineni, Osei Poku, Ronald D. Blanton:
  A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. 1-10
  
• Le Jin, Hosam Haggag, Randall L. Geiger, Degang Chen:
  Testing of Precision DACs Using Low-Resolution ADCs with Dithering. 1-10
  
• Joseph Kwan, Qing Zhao:
  A Novel Ganged DAC Solution for Multi-Site Testing. 1-6
  
• Fang Xu:
  Perfect data reconstruction algorithm of time interleaved ADCs. 1-6
  
• Toai Vo, Zhiyuan Wang, Ted Eaton, Pradipta Ghosh, Huai Li, Young Lee, Weili Wang, Hong Shin Jun, Rong Fang, Dan Singletary, Xinli Gu:
  Design for Board and System Level Structural Test and Diagnosis. 1-10
  
• Hyunbean Yi, Jaehoon Song, Sungju Park:
  Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains. 1-7
  
• Frans de Jong, Alex S. Biewenga:
  SiP-TAP: JTAG for SiP. 1-10
  
• Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin:
  Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. 1-10
  
• Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota:
  Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk. 1-9
  
• Shideh Shahidi, Sandeep K. Gupta:
  Estimating Error Rate during Self-Test via One's Counting. 1-9
  
• P. J. Tan, Tung Le, Keng-Hian Ng, Prasad Mantri, James Westfall:
  Testing of UltraSPARC T1 Microprocessor and its Challenges. 1-10
  
• Teresa L. McLaurin:
  The Challenge of Testing the ARM CORTEX-A8/sup TM/ Microprocessor Core. 1-10
  
• Tung Pham, Brian Koehler, Daniel Young, Louis Bushard:
  Test Structure and Testing of the Microsoft XBOX 360/sup TM/ Processor High Speed Front Side Bus. 1-6
  
• Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
  Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. 1-10
  
• Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu:
  A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. 1-10
  
• Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger:
  Power Supply Noise in Delay Testing. 1-10
  
• Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
  X-Press Compactor for 1000x Reduction of Test Data. 1-10
  
• Yung-Chieh Lin, Kwang-Ting Cheng:
  A Unified Approach to Test Generation and Test Data Volume Reduction. 1-10
  
• Mehdi Baradaran Tahoori, Subhasish Mitra:
  Test Compression for FPGAs. 1-9
  
• Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
  Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs. 1-10
  
• Naresh K. Bhatti, Ronald D. Blanton:
  Diagnostic Test Generation for Arbitrary Faults. 1-9
  
• Soumitra Bose, Vishwani D. Agrawal:
  Fault Coverage Estimation for Non-Random Functional Input Sequences. 1-10
  
• Robert Edmondson, Gregory Iovino, Richard Kacprowicz:
  Optimizing the Cost of Test at Intel Using per Device Data. 1-8
  
• Sylvain Tourangeau, Bill Eklow:
  Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics. 1-9
  
• Scott Davidson, Anthony P. Ambler, Helen Davidson:
  Behavioral Test Economics. 1-9
  
• Stefan Vock, Markus Schmid, Hans Martin von Staudt:
  Test Software Generation Productivity and Code Quality Improvement by applying Software Engineering Techniques. 1-8
  
• Eric Liau Chee Hong, Manfred Menke, Thomas Janik, Doris Schmitt-Landsiedel:
  Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing. 1-10
  
• Takahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma:
  A Study of Per-Pin Timing Jitter Scope. 1-7
  
• Venkat Kalyanaraman, Bruce C. Kim, Pramodchandran N. Variyam, Sasikumar Cherubal:
  DIBPro: Automatic Diagnostic Program Generation Tool. 1-8
  
• Zahi S. Abuhamdeh, Philip Pears, Jeff Remmers, Alfred L. Crouch, Bob Hannagan:
  Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks. 1-8
  
• David E. Lackey:
  Efficient Latch and Clock Structures for System-on-Chip Test Flexibility. 1-7
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. 1-10
  
• Yu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li:
  Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis. 1-9
  
• Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen:
  Diagnosis with Limited Failure Information. 1-10
  
• Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman:
  Improving Precision Using Mixed-level Fault Diagnosis. 1-10
  
• Avijit Dutta, Nur A. Touba:
  Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. 1-9
  
• Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
  A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. 1-8
  
• Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo:
  Test Data Compression of 100x for Scan-Based BIST. 1-10
  
• Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham:
  HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. 1-7
  
• Xiaoding Chen, Michael S. Hsiao:
  Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation. 1-10
  
• Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty:
  A Study of Implication Based Pseudo Functional Testing. 1-10
  
• Hiren D. Thacker, James D. Meindl:
  Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects. 1-7
  
• A. M. Majid, David C. Keezer, Jayasanker Jayabalan, Mihai Rotaru:
  Multi-Gigahertz Testing of Wafer-Level Packaged Devices. 1-10
  
• Fengming Zhang, Warren Necoechea:
  ISI Injection Filter Designs Using PIN and Varactor Diodes for SerDes Testing on ATE. 1-7
  
• Mack W. Riley, Nathan Chelstrom, Mike Genden, Shoji Sawamura:
  Debug of the CELL Processor: Moving the Lab into Silicon. 1-9
  
• Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
  Embedded Memory Diagnosis: An Industrial Workflow. 1-9
  
• Jitendra Khare, Amit B. Shah, Ashok Raman, Girish Rayas:
  Embedded Memory Field Returns - Trials and Tribulations. 1-6
  
• Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz:
  A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. 1-10
  
• Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins:
  Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues. 1-7
  
• Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham:
  Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. 1-9
  
• Sadok Aouini, Gordon W. Roberts:
  A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE. 1-10
  
• Hongjoong Shin, Joonsung Park, Jacob A. Abraham:
  Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method. 1-10
  
• Le Jin, Degang Chen, Randall L. Geiger:
  Linearity Test of Analog-to-Digital Converters Using Kalman Filtering. 1-9
  
• Chong Zhao, Sujit Dey:
  Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits. 1-10
  
• Subhasish Mitra, Ming Zhang, Saad Waqas, Norbert Seifert, Balkaran S. Gill, Kee Sup Kim:
  Combinational Logic Soft Error Correction. 1-9
  
• Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris:
  Seamless Integration of SER in Rewiring-Based Design Space Exploration. 1-9
  
• Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
  A Framework of High-quality Transition Fault ATPG for Scan Circuits. 1-6
  
• Leonard Lee, Li-C. Wang:
  An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space. 1-10
  
• Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
  Exact At-speed Delay Fault Grading in Sequential Circuits. 1-10
  
• Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich:
  At-Speed Structural Test For High-Performance ASICs. 1-10
  
• Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar:
  On-chip Test and Repair of Memories for Static and Dynamic Faults. 1-10
  
• Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen:
  A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. 1-9
  
• Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin:
  An Enhanced EDAC Methodology for Low Power PSRAM. 1-10
  
• Jeffrey L. Roehr:
  Very-Low Voltage (VLV) and VLV Ratio (VLVR) Testing for Quality, Reliability, and Outlier Detection. 1-6
  
• Liquan Fang, Mohammed Lemnawar, Yizi Xing:
  Cost Effective Outliers Screening with Moving Limits and Correlation Testing for Analogue ICs. 1-10
  
• Doug Heaberlin:
  The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution. 1-10
  
• Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng:
  Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling. 1-10
  
• Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. 1-10
  
• Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
  BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. 1-8
  
• Erdem Serkan Erdogan, Sule Ozev:
  A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise. 1-10
  
• N. Vijayaraghavan, Balwant Singh, Saurabh Singh, Vishal Srivastava:
  Novel Architecture for On-Chip AC Characterization of I/Os. 1-10
  
• Mitchell Lin, Kwang-Ting Cheng:
  Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links. 1-10
  
• Wei Pei, Wen-Ben Jone, Yiming Hu:
  Fault Modeling and Detection for Drowsy SRAM Caches. 1-10
  
• Rahul Nadkarni, Igor Arsovski, Reid Wistort, Valerie Chickanosky:
  Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories. 1-9
  
• Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath:
  DRAM-Specific Space of Memory Tests. 1-10
  
• Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao:
  Testing MRAM for Write Disturbance Fault. 1-9
  
• Martin Dresler:
  Technique to Detect RF Interface and Contact Issues During Production Testing. 1-6
  
• Frank Demmerle:
  Integrated RF-CMOS Transceivers challenge RF Test. 1-8
  
• Sofiane Ellouz, Patrice Gamand, Christophe Kelma, Bertrand Vandewiele, Bruno Allard:
  Combining Internal Probing with Artificial Neural Networks for Optimal RFIC Testing. 1-9
  
• Selim Sermet Akbay, Jose L. Torres, Julie M. Rumer, Abhijit Chatterjee, Joel Amtsfield:
  Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation. 1-10
  
• Heiko Ehrenberg:
  IEEE P1581 - Getting More Board Test Out of Boundary Scan. 1-10
  
• Bambang Suparjo, Adam W. Ley, Adam Cron, Heiko Ehrenberg:
  Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test. 1-9
  
• Rosa D. Reinosa:
  Lead Free Through Hole Technology (THT) and Contact Repeatability in In-Circuit Test. 1-10
  
• Madhavan Doraiswamy, James J. Grealish:
  Implementation of Solder-bead Probing in High Volume Manufacturing. 1-10
  
• Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka:
  Multi Strobe Circuit for 2.133GHz Memory Test System. 1-9
  
• Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
  A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement. 1-8
  
• Jochen Rivoir:
  Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration. 1-10
  
• Lucy Liu, Eddie Lew:
  Periodic Jitter Amplitude Calibration with Walking Strobe. 1-8
  
• Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware:
  A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. 1-10
  
• Mehrdad Nourani, Arun Radhakrishnan:
  Modeling and Testing Process Variation in Nanometer CMOS. 1-10
  
• Thomas Nirmaier, Wolfgang Spirkl, Eric Liau Chee Hong:
  Fully automated semiconductor operating condition testing. 1-9
  
• Ajay Khoche, Domenico Chindamo, Michael Braun, Martin Fischer:
  Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics. 1-10
  
• Nishant Patil, Subhasish Mitra, Steven S. Lumetta:
  Signature Analyzer Design for Yield Learning Support. 1-10
  
• Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill:
  Signature Based Diagnosis for Logic BIST. 1-9
  
• Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar:
  An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. 1-10
  
• Mohamed Hafed, Daniel Watkins, Clarence Tam, Bardia Pishdad:
  Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules. 1-10
  
• Dongwoo Hong, Kwang-Ting Cheng:
  Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links. 1-10
  
• Stephen K. Sunter, Aubin Roy:
  Structural Tests for Jitter Tolerance in SerDes Receivers. 1-10
  
• Peter Maxwell:
  The Design, Implementation and Analysis of Test Experiments. 1-9
  
• François-Fabien Ferhani, Edward J. McCluskey:
  Classifying Bad Chips and Ordering Test Sets. 1-10
  
• Eric Johnson:
  Structural Testing of High-Speed Serial Buses: A Case Study Analysis. 1-9
  
• Jeff Rearick:
  A Survey of Test Problems and Solutions. 1-10
  
• Chris Allsup:
  The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time. 1-9
  
• Roger Nicholson, Cathy Kardach, Bruce Cory:
  The Role of ATPG Fault Diagnostics in Driving Physical Analysis. 1-7
  
• Rajesh Raina:
  What is DFM & DFY and Why Should I Care ? 1-9
  
• Robert C. Aitken:
  The Design and Validation of IP for DFM/DFY Assurance. 1-7
  
• Anne Gattiker, Manjul Bhushan, Mark B. Ketchen:
  Data Analysis Techniques for CMOS Technology Characterization and Product Impact Assessment. 1-10
  
• Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, J.-F. Cote:
  IEEE P1687: Toward Standardized Access of Embedded Instrumentation. 1-8
  
• Ilka Reis, Peter Collins, Marc van Houcke:
  On-line Boundary-Scan Testing in Service of Extended Products. 1-10
  
• Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie:
  OCI: Open Compression Interface. 1-4
  

Last update Sat May 18 19:10:43 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page