LCTES 2004: Washington, DC, USA

Evaluating embedded applications

• Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
  GraalBench: a 3D graphics benchmark suite for mobile phones. 1-9
  
• Thomas Martin, Mark T. Jones, Joshua Edmison, Tanwir Sheikh, Zahi Nakad:
  Modeling and simulating electronic textile applications. 10-19
  
• Paul Willmann, Michael Brogioli, Vijay S. Pai:
  Spinach: a liberty-based simulator for programmable network interface architectures. 20-29
  

Languages and software architectures

• Christopher L. Conway, Stephen A. Edwards:
  NDL: a domain-specific language for device drivers. 30-36
  
• Nagendra J. Kumar, Siddhartha Shivshankar, Alexander G. Dean:
  Asynchronous software thread integration for efficient software. 37-46
  
• Wei Qin, Subramanian Rajagopalan, Sharad Malik:
  A formal concurrency model based architecture description language for synthesis of software development tools. 47-56
  

Power management I

• Ravindra Jejurikar, Rajesh K. Gupta:
  Procrastination scheduling in fixed priority real-time systems. 57-66
  
• Xiaotong Zhuang, Santosh Pande:
  Power-efficient prefetching via bit-differential offset assignment on embedded processors. 67-77
  
• Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin:
  Speculative software management of datapath-width for energy optimization. 78-87
  
• Chaeseok Im, Soonhoi Ha:
  Dynamic voltage scaling for real-time multi-task scheduling using buffers. 88-94
  

Power management II

• Lian Li, Jingling Xue:
  A trace-based binary compilation framework for energy-aware computing. 95-106
  
• James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois:
  ESys.Net: a new solution for embedded systems modeling and simulation. 107-114
  
• Gilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh:
  XTREM: a power simulator for the Intel XScale® core. 115-125
  

Caches and instructions sets

• Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies:
  Feedback driven instruction-set extension. 126-135
  
• Kaustubh Patil, Kiran Seth, Frank Mueller:
  Compositional static instruction cache simulation. 136-145
  
• Johan Stärner, Lars Asplund:
  Measuring the cache interference cost in preemptive real-time systems. 146-154
  

Code management

• Lingli Zhang, Chandra Krintz:
  Adaptive code unloading for resource-constrained JVMs. 155-164
  
• Peng Li, Steve Zdancewic:
  Advanced control flow in Java card programming. 165-174
  
• Jia Zeng, Cristian Soviani, Stephen A. Edwards:
  Generating fast code from concurrent program dependence graphs. 175-181
  

Register allocation

• Jason Hiser, Jack W. Davidson:
  EMBARC: an efficient memory bank assignment algorithm for retargetable compilers. 182-191
  
• Xiaotong Zhuang, Tao Zhang, Santosh Pande:
  Hardware-managed register allocation for embedded processors. 192-201
  
• Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana:
  A retargetable register allocation framework for embedded processors. 202-210
  

Compilers and optimization

• Bruno De Bus, Bjorn De Sutter, Ludo Van Put, Dominique Chanet, Koen De Bosschere:
  Link-time optimization of ARM binaries. 211-220
  
• Bernhard Scholz, R. Nigel Horspool, Jens Knoop:
  Optimizing for space and time usage with speculative partial redundancy elimination. 221-230
  
• L. Almagor, Keith D. Cooper, Alexander Grosul, Timothy J. Harvey, Steven W. Reeves, Devika Subramanian, Linda Torczon, Todd Waterman:
  Finding effective compilation sequences. 231-239
  

Software

• Hendra Saputra, Guangyu Chen, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
  Code protection for resource-constrained embedded devices. 240-248
  
• Zhi Guo, Betul Buyukkurt, Walid A. Najjar:
  Input data reuse in compiling window operations onto reconfigurable hardware. 249-256
  
• Andrzej Wasowski:
  Flattening statecharts without explosions. 257-266