LCTES 2006: Ottawa, Ontario, Canada

• Margaret Martonosi:
  Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences. 1
  

Mobile applications

• Carl von Platen, Johan Eker:
  Feedback linking: optimizing object code layout for updates. 2-11
  
• Kun Zhang, Santosh Pande:
  Minimizing downtime in seamless migrations of mobile applications. 12-21
  
• Michal Spivak, Sivan Toledo:
  Storing a persistent transactional object heap on flash memory. 22-33
  

Program analysis

• John Regehr, Usit Duongsaa:
  Deriving abstract transfer functions for analyzing embedded software. 34-43
  
• Nathan Cooprider, John Regehr:
  Pluggable abstract domains for analyzing embedded software. 44-53
  
• Antoine Miné:
  Field-sensitive value analysis of embedded C programs with union types and pointer arithmetics. 54-63
  

Compilation

• William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson:
  Reducing the cost of conditional transfers of control by using comparison specifications. 64-71
  
• Xiaotong Zhuang, Santosh Pande:
  Effective thread management on network processors with compiler analysis. 72-82
  
• Prasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson:
  In search of near-optimal optimization phase orderings. 83-92
  

Real-time techniques

• Klaus Danne, Marco Platzner:
  An EDF schedulability test for periodic tasks on reconfigurable hardware devices. 93-102
  
• Christer Sandberg, Andreas Ermedahl, Jan Gustafsson, Björn Lisper:
  Faster WCET flow analysis by program slicing. 103-112
  
• Steffen Prochnow, Claus Traulsen, Reinhard von Hanxleden:
  Synthesizing safe state machines from Esterel. 113-124
  

Code generation

• Stephen A. Edwards, Olivier Tardieu:
  Efficient code generation from SHIM models. 125-134
  
• Tom Rothamel, Yanhong A. Liu, Constance L. Heitmeyer, Elizabeth I. Leonard:
  Generating optimized code from SCR specifications. 135-144
  
• Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner:
  Effective compiler generation by architecture description. 145-152
  

Low power issues

• Jian-Jia Chen, Tei-Wei Kuo:
  Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor. 153-162
  
• Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
  Compiler-directed thermal management for VLIW functional units. 163-172
  
• Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie:
  Bypass aware instruction scheduling for register file power reduction. 173-181
  

Tools

• Leipo Yan, Thambipillai Srikanthan, Niu Gang:
  Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures. 182-188
  
• Raju Pandey, Jeffrey Wu:
  BOTS: a constraint-based component system for synthesizing scalable software systems. 189-198
  
• Weihua Zhang, Xinglong Qian, Ye Wang, Binyu Zang, Chuanqi Zhu:
  Optimizing compiler for shared-memory multiple SIMD architecture. 199-208