28. MICRO 1995: Ann Arbor, Michigan, USA

• Nicholas C. Gloy, Michael D. Smith, Cliff Young:
  Performance issues in correlated branch prediction schemes. 3-14
  
• Ravi Nair:
  Dynamic path-based branch correlation. 15-23
  
• Brad Calder, Dirk Grunwald, Amitabh Srivastava:
  The predictability of branches in libraries. 24-34
  
• Pritpal S. Ahuja, Douglas W. Clark, Anne Rogers:
  The performance impact of incomplete bypassing in processor pipelines. 36-45
  
• Vasanth Bala, Norman Rubin:
  Efficient instruction scheduling using finite state automata. 46-56
  
• Michael S. Schlansker, Vinod Kathail:
  Critical path reduction for scalar programs. 57-69
  
• Andrew S. Huang, John Paul Shen:
  A limit study of local memory requirements using value reuse profiles. 71-81
  
• Todd M. Austin, Gurindar S. Sohi:
  Zero-cycle loads: microarchitecture support for reducing load latency. 82-92
  
• Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
  A modified approach to data cache management. 93-103
  
• Vicki H. Allan, U. R. Shah, K. M. Reddy:
  Petri net versus modulo scheduling for software pipelining. 105-110
  
• Nancy J. Warter-Perez, Noubar Partamian:
  Modulo scheduling with multiple initiation intervals. 111-119
  
• B. Natarajan, Michael S. Schlansker:
  Spill-free parallel scheduling of basic blocks. 119-124
  
• Jack W. Davidson, Sanjay Jinturkar:
  Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation. 125-132
  
• John R. Gurd, David F. Snelling:
  Self-regulation of workload in the Manchester Data-Flow computer. 135-145
  
• Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee:
  The M-Machine multicomputer. 146-156
  
• Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau:
  Region-based compilation: an introduction and motivation. 158-168
  
• Cindy Norris, Lori L. Pollock:
  An experimental study of several cooperative register allocation and instruction scheduling strategies. 169-179
  
• Alexandre E. Eichenberger, Edward S. Davidson:
  Register allocation for predicated code. 180-191
  
• Barry S. Fagin, Kathryn Russell:
  Partial resolution in branch target buffers. 193-198
  
• Brad Calder, Dirk Grunwald, Joel S. Emer:
  A system level perspective on branch architecture performance. 199-206
  
• Thomas M. Conte, Sumedh W. Sathaye:
  Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. 208-218
  
• Mark Smotherman, Manoj Franklin:
  Improving CISC instruction decoding performance using a fill unit. 219-229
  
• Mikko H. Lipasti, William J. Schmidt, Steven R. Kunkel, Robert R. Roediger:
  SPAID: software prefetching in pointer- and call-intensive environments. 231-236
  
• Tien-Fu Chen:
  An effective programmable prefetch engine for on-chip caches. 237-242
  
• Toshihiro Ozawa, Yasunori Kimura, Shin'ichiro Nishizaki:
  Cache miss heuristics and preloading techniques for general-purpose programs. 243-248
  
• Po-Yung Chang, Eric Hao, Yale N. Patt:
  Alternative implementations of hybrid branch predictors. 252-257
  
• Simonjit Dutta, Manoj Franklin:
  Control flow prediction with tree-like subgraphs for superscalar processors. 258-263
  
• Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge:
  The role of adaptivity in two-level adaptive branch prediction. 264-269
  
• Lucas Roh, Walid A. Najjar:
  Design of storage hierarchy in multithreaded architectures. 271-278
  
• Stéphan Jourdan, Pascal Sainrat, Daniel Litaize:
  An investigation of the performance of various instruction-issue buffer topologies. 279-284
  
• Subbarao Palacharla, James E. Smith:
  Decoupling integer execution in superscalar processors. 285-290
  
• Luis A. Lozano, Guang R. Gao:
  Exploiting short-lived variables in superscalar processors. 292-302
  
• Johan Janssen, Henk Corporaal:
  Partitioned register file for TTAs. 303-312
  
• Augustus K. Uht, Vijay Sindagi, Kelley Hall:
  Disjoint eager execution: an optimal form of speculative execution. 313-325
  
• Daniel M. Lavery, Wen-mei W. Hwu:
  Unrolling-based optimizations for modulo scheduling. 327-337
  
• Alexandre E. Eichenberger, Edward S. Davidson:
  Stage scheduling: a technique to reduce the register requirements of a modulo schedule. 338-349
  
• Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
  Hypernode reduction modulo scheduling. 350-360
  

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