34. MICRO 2001: Austin, Texas, USA

Keynote

• Harvey G. Cragon, Ernest Cockrell Jr.:
  Fifty years of microarchitecture. 2
  

Novel ideas

• Chen-Yong Cher, T. N. Vijaykumar:
  Skipper: a microarchitecture for exploiting control-flow independence. 4-15
  
• Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta:
  Performance characterization of a hardware mechanism for dynamic optimization. 16-27
  
• Eric Rotenberg:
  Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. 28-39
  
• Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler:
  A design space evaluation of grid processor architectures. 40-51
  

Memory hierarchies

• Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy:
  Reducing set-associative cache energy via way-prediction and selective direct-mapping. 54-65
  
• Yuan Xie, Wayne Wolf, Haris Lekatsas:
  A code decompression architecture for VLIW processors. 66-75
  
• Byung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai:
  Direct load: dependence-linked dataflow resolution of load address and cache coordinate. 76-87
  

Energy efficient architectures

• Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose:
  Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. 90-101
  
• Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai:
  Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. 102-113
  
• John S. Seng, Eric Tune, Dean M. Tullsen:
  Reducing power with dynamic critical path information. 114-123
  
• Emmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic:
  Direct addressed caches for reduced power consumption. 124-133
  

Keynote

• Andrew Wolfe:
  Emerging applications for the connected home. 136
  

Modulo scheduling

• Matthew C. Merten, Wen-mei W. Hwu:
  Modulo schedule buffers. 138-149
  
• Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González:
  Graph-partitioning based instruction scheduling for clustered processors. 150-159
  
• Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
  Modulo scheduling with integrated register spilling for clustered VLIW architectures. 160-169
  

Compilation

• Artour Stoutchinin, François de Ferrière:
  Efficient static single assignment form for predication. 172-181
  
• Youngsoo Choi, Allan D. Knies, Luke Gerke, Tin-Fook Ngai:
  The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor. 182-191
  
• Gary William Grewal, Thomas Charles Wilson:
  Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). 192-202
  

Superscalar architectures

• Mary D. Brown, Jared Stark, Yale N. Patt:
  Select-free instruction scheduling logic. 204-213
  
• Joydeep Ray, James C. Hoe, Babak Falsafi:
  Dual use of superscalar datapath for transient-fault detection and recovery. 214-224
  
• Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori:
  A high-speed dynamic instruction scheduling scheme for superscalar processors. 225-236
  
• Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
  Reducing the complexity of the register file in dynamic superscalar processors. 237-248
  

Multimedia and graphics

• Christopher J. Hughes, Jayanth Srinivasan, Sarita V. Adve:
  Saving energy with architectural and frequency adaptations for multimedia applications. 250-261
  
• John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu:
  Enhancing loop buffering of media and telecommunications applications using low-overhead predication. 262-273
  
• Osman S. Unsal, Raksit Ashok, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
  Cool-cache for hot multimedia. 274-283
  
• Emile Hsieh, Vladimir Pentkovski, Thomas Piazza:
  ZR: a 3D API transparent technology for chunk rendering. 284-291
  

Multithreading and value prediction

• Ravi Rajwar, James R. Goodman:
  Speculative lock elision: enabling highly concurrent multithreaded execution. 294-305
  
• Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen:
  Dynamic speculative precomputation. 306-317
  
• Dean M. Tullsen, Jeffery A. Brown:
  Handling long-latency loads in a simultaneous multithreading processor. 318-327
  
• Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti:
  Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. 328-337
  

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