37. MICRO 2004: Portland, Oregon, USA

Keynote 1

• Shekhar Y. Borkar: Microarchitecture and Design Challenges for Gigascale Integration. 3

Instruction Collapsing

• Peter G. Sassone, D. Scott Wills:
  Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication. 7-17
  
• Anne Bracy, Prashant Prahlad, Amir Roth:
  Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth. 18-29
  
• Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner:
  Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization. 30-40
  

Performance Evaluation

• Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam:
  MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms. 43-54
  
• Martin Burtscher, Ilya Ganusov:
  Automatic Synthesis of High-Speed Processor Simulators. 55-66
  
• Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha:
  Thermal Modeling, Characterization and Management of On-Chip Networks. 67-78
  

Trace Analysis

• Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi:
  Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. 81-92
  
• Murali Annavaram, Ryan Rakvic, Marzia Polito, Jean-Yves Bouguet, Richard A. Hankins, Bob Davies:
  The Fuzzy Correlation between Code and Performance Predictability. 93-104
  
• Xiangyu Zhang, Rajiv Gupta:
  Whole Execution Traces. 105-116
  

Control Flow

• David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt:
  Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. 119-128
  
• Jamison D. Collins, Dean M. Tullsen, Hong Wang:
  Control Flow Optimization Via Dynamic Reconvergence Prediction. 129-140
  

Keynote 2

• Gurindar S. Sohi: Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. 143

Adaptive Microarchitectures

• Arindam Mallik, Gokhan Memik:
  A Case for Clumsy Packet Processors. 147-156
  
• Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott:
  Dynamically Trading Frequency for Complexity in a GALS Microprocessor. 157-168
  

Multithreaded/Multicore Processors

• Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández:
  Dynamically Controlled Resource Allocation in SMT Processors. 171-182
  
• Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder:
  Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy. 183-194
  
• Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen:
  Conjoined-Core Chip Multiprocessing. 195-206
  

Security

• Nathan Tuck, Brad Calder, George Varghese:
  Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow. 209-220
  
• Jedidiah R. Crandall, Frederic T. Chong:
  Minos: Control Data Attack Prevention Orthogonal to Memory Model. 221-232
  
• Milenko Drinic, Darko Kirovski:
  A Hardware-Software Platform for Intrusion Prevention. 233-242
  
• Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August:
  RIFLE: An Architectural Framework for User-Centric Information-Flow Security. 243-254
  

Reliability

• Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi:
  Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. 257-268
  
• Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas:
  AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. 269-280
  

Code Generation and Optimization

• Ghassan Shobaki, Kent D. Wilken:
  Optimal Superblock Scheduling Using Enumeration. 283-293
  
• Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li:
  Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. 294-303
  
• Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev:
  Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. 304-315
  

Caches and Memory

• Bradford M. Beckmann, David A. Wood:
  Managing Wire Delay in Large Chip-Multiprocessor Caches. 319-330
  
• Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic:
  Cache Refill/Access Decoupling for Vector Machines. 331-342
  
• Ibrahim Hur, Calvin Lin:
  Adaptive History-Based Memory Schedulers. 343-354
  
• Scott Rixner:
  Memory Controller Optimizations for Web Servers. 355-366