MTDT 2006: Taipei, Taiwan

Introduction

• Foreword.
  
• Organizing Committee.
  
• Program Committee.
  
• Reviewers.
  

Reception Talk

• Pei-Lin Pai:
  DRAM Industry Trend.
  

Keynote Speech 1

• Riichiro Shirota:
  Roadmap of the Flash Memory.
  

Keynote Speech 2

• Chih-Yuan Lu:
  Non-volatile Semiconductor Memory Technology in Nanotech Era.
  

Invited Talk 1

• Charles Hsu:
  Future Prospective of Programmable Logic Non-volatile Device.
  

Invited Talk 2

• Jordan Lai:
  SRAM Design Techniques for Sub-nano CMOS Technology.
  

Invited Talk 3

• Peter Muhmenthaler:
  New on-Chip DFT and ATE Features for Efficient Embedded Memory Test.
  

Embedded Tutorial

• Mohamed Azimane:
  High-Quality Memory Test.
  

Session T1: Memory Diagnosis & Repair

• Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu:
  Fault-Pattern Oriented Defect Diagnosis for Flash Memory. 3-8
  
• T. A. Gyonjyan, Gurgen Harutunyan, Valery A. Vardanian:
  A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults. 9-14
  
• Hsing-Chung Liang, Le-Quen Tzeng:
  Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories. 15
  

Session T2: Memory Device & Organization

• Jyi-Tsong Lin, Mike Chang:
  A New 1T DRAM Cell With Enhanced Floating Body Ef. 23-27
  
• Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu:
  FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. 28-33
  
• Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng:
  Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. 34-42
  

Session V2: Memory Design and Testing (Invited)

• Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa:
  MRAM Write Error Categorization with QCKB. 43-48
  
• Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson:
  DDR2 DRAM Output Timing Optimization. 49-54
  
• Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev:
  Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. 55-64
  

Session T3: Flash & SRAM Characterization

• Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou:
  SRAM Cell Current in Low Leakage Design. 65-70
  
• Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene:
  On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components. 71-76
  
• Victor Chao-Wei Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, Liang-Tai Kuo, Shi-Hsien Chen, Houng-Chi Wei, Hann-Ping Hwang, Saysamone Pittikoun:
  Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash Memory. 77-79
  
• Jia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shih-Hsien Chen, Hann-Ping Hwang, Saysamone Pittikoun, Travis Cho, Chin-Hsing Kao:
  Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash Memory. 80-84