8. MTV 2007: Austin, TX, USA

Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (Eds.): Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA. IEEE Computer Society 2007, ISBN 978-0-7695-3241-7

Power Analysis

Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar:
Assertion-Based Modal Power Estimation. 3-7
Dam Sunwoo, Hassan Al-Sukhni, Jim Holt, Derek Chiou:
Early Models for System-Level Power Estimation. 8-14
Wang-Dauh Tseng, Lung-Jen Lee:
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering. 15-21

Formal Methods

Sandip Ray, Warren A. Hunt Jr.:
Mechanized Certification of Secure Hardware Designs. 25-32
Marc Herbstritt, Vanessa Struve, Bernd Becker:
Application of Lifting in Partial Design Analysis. 33-38
Gaurav Singh, Sandeep K. Shukla:
Model Checking Bluespec Specified Hardware Designs. 39-43
Selma Ikiz, Alper Sen:
Runtime Verification of k-Mutual Exclusion for SoCs. 44-50
Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil:
A Scalable Symbolic Simulator for Verilog RTL. 51-59

System Level Validation and Test

Subir K. Roy:
Top Level SOC Interconnectivity Verification Using Formal Techniques. 63-70
Danilo Ravotto, E. Sanchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction. 71-76
W. Di Palma, Danilo Ravotto, E. Sanchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero:
Automotive Microcontroller End-of-Line Test via Software-Based Methodologies. 77-82

Functional Validation and ATPG

Tommy Bojan, Igor Frumkin, Robert Mauri:
Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning. 85-90
Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
Chico: An On-chip Hardware Checker for Pipeline Control Logic. 91-97
Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris:
A CLP-Based Functional ATPG for Extended FSMs. 98-105

AMS Verification

Scott Little, Alper Sen, Chris J. Myers:
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. 109-115
Wei Qin, Asa Ben-Tzur, Boris Gutkovich:
An ADL for Functional Specification of IA32. 119-127
Mark Nodine:
Automatic Testbench Generation for Rearchitected Designs. 128-136