1. NOCS 2007: Princeton, New Jersey, USA

Keynote 1

• William J. Dally:
  Enabling Technology for On-Chip Interconnection Networks. 3
  

NoC Design Case Studies

• Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
  Implementation and Evaluation of a Dynamically Routed Processor Operand Network. 7-17
  
• Thomas William Ainsworth, Timothy Mark Pinkston:
  On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus. 18-29
  
• Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee, Hoi-Jun Yoo:
  Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. 30-39
  
• Jeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka:
  Architecture of the Scalable Communications Core. 40-52
  

Technology and Circuit Technologies

• Assaf Shacham, Keren Bergman, Luca P. Carloni:
  On the Design of a Photonic Network-on-Chip. 53-64
  
• Crescenzo D'Alessandro, Nikolaos Minas, Keith Heron, David Kinniment, Alexandre Yakovlev:
  NoC Communication Strategies Using Time-to-Digital Conversion. 65-74
  
• Shuming Chen, Xiangyuan Liu:
  A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs. 75-82
  
• Ivan Miro Panades, Alain Greiner:
  Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. 83-94
  

System Architecture, Verification and Debug

• Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek:
  Transaction-Based Communication-Centric Debug. 95-106
  
• Théodore Marescaux, Erik Brockmeyer, Henk Corporaal:
  The Impact of Higher Communication Layers on NoC Supported MP-SoCs. 107-116
  
• Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
  The Power of Priority: NoC Based Distributed Cache Coherency. 117-126
  
• Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz:
  A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. 127-136
  
• Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
  Access Regulation to Hot-Modules in Wormhole NoCs. 137-148
  

Keynote 2

• Giovanni De Micheli:
  Design Technologies for Networks on Chips. 149
  

Routing and Topology

• George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis:
  Approaching Ideal NoC Latency with Pre-Configured Routes. 153-162
  
• Arnab Banerjee, Robert D. Mullins, Simon W. Moore:
  A Power and Energy Exploration of Network-on-Chip Architectures. 163-172
  
• Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
  A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. 173-182
  
• Jose Flich, Andres Mejia, Pedro López, José Duato:
  Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips. 183-194
  
• Stephan Bourduas, Zeljko Zilic:
  A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. 195-204
  

Panel

• Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu:
  Towards Open Network-on-Chip Benchmarks. 205
  

Posters

• Per Badlund, Axel Jantsch:
  An Analytical Approach for Dimensioning Mixed Traffic Networks. 215
  
• Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach:
  Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. 216
  
• Mikael Millberg, Axel Jantsch:
  A Study of NoC Exit Strategies. 217
  
• Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon:
  QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. 218
  
• Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini:
  Reducing Interconnect Cost in NoC through Serialized Asynchronous Links. 219
  
• Sheng Xu, Ibis Benito, Wayne P. Burleson:
  Thermal Impacts on NoC Interconnects. 220
  

Reconfigurable NoCs

• Jean-Philippe Diguet, Samuel Evain, Romain Vaslin, Guy Gogniat, Emmanuel Juin:
  NOC-centric Security of Reconfigurable SoC. 223-232
  
• Andreas Hansson, Kees Goossens:
  Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. 233-242
  
• Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
  Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. 243-252
  
• Roman Gindin, Israel Cidon, Idit Keidar:
  NoC-Based FPGA: Architecture and Routing. 253-264
  

Dinner Speaker

• Drew Wingard:
  Reflections on 10 Years as a Commercial On-Chip Interconnect Provider. 265
  

Keynote 3

• Israel Cidon:
  NoC: Network or Chip? 269
  

CAD and Methodology for NoCs

• Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini:
  NoC Design and Implementation in 65nm Technology. 273-282
  
• Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore:
  Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. 283-294
  
• Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet:
  ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. 295-306
  

NoC Mapping and Simulation

• Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud:
  Implementing DSP Algorithms with On-Chip Networks. 307-316
  
• Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu:
  A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. 317-322
  
• Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit:
  Fast, Accurate and Detailed NoC Simulations. 323-332