2. NOCS 2008: Newcastle University, UK

• David May:
  Invited Talk 1- Past, Present, and Future Communicating Processors.
  
• Ian H. White, Richard V. Penty:
  Invited Talk 2 - Optical Interconnects for Backplane and Chip-to-Chip Photonics.
  
• Bart Vermeulen, Kees Goossens, Siddharth Umrani:
  Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. 3-12
  
• Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston:
  A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. 13-22
  
• Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano:
  Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. 23-32
  
• Rosemary M. Francis, Simon W. Moore, Robert D. Mullins:
  A Network of Time-Division Multiplexed Wiring for FPGAs. 35-44
  
• Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah:
  Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. 45-54
  
• Mikkel Bystrup Stensgaard, Jens Sparsø:
  ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. 55-64
  
• Alireza Ejlali, Bashir M. Al-Hashimi:
  SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks. 67-76
  
• Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang:
  Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. 77-83
  
• Jose Flich, Samuel Rodrigo, José Duato:
  An Efficient Implementation of Distributed Routing Algorithms for NoCs. 87-96
  
• Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
  Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. 97-106
  
• Francisco Gilabert Villamón, Simone Medardoni, Davide Bertozzi, Luca Benini, María Engracia Gómez, Pedro López, José Duato:
  Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 107-116
  
• Bin Li, Li-Shiuan Peh, Priyadarsan Patra:
  Impact of Process and Temperature Variations on Network-on-Chip Design Exploration. 117-126
  
• Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet:
  Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. 129-138
  
• Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner:
  Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. 139-148
  
• Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach:
  A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. 149-158
  
• Zheng Shi, Alan Burns:
  Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching. 161-170
  
• Itamar Cohen, Ori Rottenstreich, Isaac Keslassy:
  Statistical Approach to NoC Design. 171-180
  
• Pablo Abad, Valentin Puente, José-Ángel Gregorio:
  Reducing the Interconnection Network Cost of Chip Multiprocessors. 183-192
  
• Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti:
  Circuit-Switched Coherence. 193-202
  
• Suboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi:
  Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network. 205-206
  
• Min Zhang, Chiu-sing Choy:
  Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip. 207-208
  
• Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth S. Stevens:
  Network Simplicity for Latency Insensitive Cores. 209-210
  
• Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij:
  Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. 211-212
  
• Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
  Implementation of Wave-Pipelined Interconnects in FPGAs. 213-214
  
• Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu:
  An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. 215-216
  
• Shijun Lin, Li Su, Depeng Jin, Lieguang Zeng:
  Dual-Channel Access Mechanism for Cost-Effective NoC Design. 217-218