14. PATMOS 2004: Santorini, Greece

@proceedings{DBLP:conf/patmos/2004,
  editor    = {Enrico Macii and
               Odysseas G. Koufopavlou and
               Vassilis Paliouras},
  title     = {Integrated Circuit and System Design, Power and Timing Modeling,
               Optimization and Simulation; 14th International Workshop, PATMOS
               2004, Santorini, Greece, September 15-17, 2004, Proceedings},
  booktitle = {PATMOS},
  publisher = {Springer},
  series    = {Lecture Notes in Computer Science},
  volume    = {3254},
  year      = {2004},
  isbn      = {3-540-23095-5},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote Speech

• Hugo De Man:
  Connecting E-Dreams to Deep-Submicron Realities. 1
  

Invited Talks

• Nick Kanopoulos:
  Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. 2
  
• Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara:
  Low-Voltage Embedded RAMs - Current Status and Future Trends. 3-15
  
• Carlo Dallavalle:
  Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing. 16
  

Embedded Tutorials

• Domenik Helms, Eike Schmidt, Wolfgang Nebel:
  Leakage in CMOS Circuits - An Introduction. 17-35
  
• Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar:
  The Certainty of Uncertainty: Randomness in Nanometer Design. 36-47
  

Buses and Communication

• Jihong Ren, Mark R. Greenstreet:
  Crosstalk Cancellation for Realistic PCB Buses. 48-57
  
• Sabino Salerno, Enrico Macii, Massimo Poncino:
  A Low-Power Encoding Scheme for GigaByte Video Interfaces. 58-68
  
• Markus Tahedl, Hans-Jörg Pfleiderer:
  Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. 69-78
  
• Mircea R. Stan, Yan Zhang:
  Perfect 3-Limited-Weight Code for Low Power I/O. 79-89
  
• Claudia Kretzschmar, Torsten Bitterlich, Dietmar Müller:
  A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses. 90-99
  

Circuits and Devices (I)

• Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
  Performance Metric Based Optimization Protocol. 100-109
  
• B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
  Temperature Dependence in Low Power CMOS UDSM Process. 110-118
  
• Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti:
  Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. 119-128
  
• Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani:
  High Yield Standard Cell Libraries: Optimization and Modeling. 129-137
  
• Gabriella Trucco, Giorgio Boselli, Valentino Liberali:
  A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits. 138-147
  

Low Power (I)

• Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger:
  Sleepy Stack Reduction of Leakage Power. 148-158
  
• Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae:
  A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. 159-168
  
• Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine:
  Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures. 169-178
  
• André K. Nieuwland, Atul Katoch, Maurice Meijer:
  Reducing Cross-Talk Induced Power Consumption and Delay. 179-188
  
• Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre:
  Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. 189-197
  
• Geoff V. Merrett, Bashir M. Al-Hashimi:
  Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. 198-207
  

Architectures

• Jie Ruan, Mark G. Arnold:
  Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS. 208-217
  
• Armin Wellig, Julien Zory, Norbert Wehn:
  Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications. 218-227
  
• Matthias Müller, Andreas Wortmann, Dominik Mader, Sven Simon:
  Register Isolation for Synthesizable Register Files. 228-237
  
• Carlo Brandolese, William Fornaciari, Fabio Salice:
  Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. 238-247
  
• Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos:
  Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. 248-257
  

Asynchronous Circuits

• Milos Krstic, Eckhard Grass:
  GALSification of IEEE 802.11a Baseband Processor. 258-267
  
• Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin:
  TAST Profiler and Low Energy Asynchronous Design Methodology. 268-277
  
• D. J. Kinniment, Alexandre Yakovlev:
  Low Latency Synchronization Through Speculation. 278-288
  
• Yijun Liu, Stephen B. Furber:
  Minimizing the Power Consumption of an Asynchronous Multiplier. 289-300
  
• Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø:
  A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. 301-310
  

System Design

• Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck:
  L0 Cluster Synthesis and Operation Shuffling. 311-321
  
• Anders Brødløs Olsen, Finn Büttner, Peter Koch:
  On Combined DVS and Processor Evaluation. 322-331
  
• Christos Drosos, Labros Bisdounis, Dimitris Metafas, Spyros Blionas, Anna Tatsaki:
  A Multi-level Validation Methodology for Wireless Network Applications. 332-341
  
• Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin:
  SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. 342-351
  
• Emanuele Lattanzi, Andrea Acquaviva, Alessandro Bogliolo:
  Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards. 352-361
  
• Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Raimundo S. Barreto, Fernando F. Carvalho:
  Towards a Software Power Cost Analysis Framework Using Colored Petri Net. 362-371
  

Circuits and Devices (II)

• Francesco Pessolano, R. I. M. P. Meijer:
  A 260ps Quasi-static ALU in 90nm CMOS. 372-380
  
• Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli:
  Embedded EEPROM Speed Optimization Using System Power Supply Resources. 381-391
  
• Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
  Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. 392-401
  
• Uri Frank, Ran Ginosar:
  A Predictive Synchronizer for Periodic Clock Domains. 402-412
  
• Jürgen Fischer, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, Doris Schmitt-Landsiedel:
  Power Supply Net for Adiabatic Circuits. 413-422
  

Interconnect and Physical Design

• Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada:
  A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. 423-432
  
• Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
  Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. 433-441
  
• Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
  An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. 442-452
  
• Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke:
  Wirelength Reduction Using 3-D Physical Design. 453-462
  
• Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
  On Skin Effect in On-Chip Interconnects. 463-470
  

Security and Safety

• Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev:
  A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits. 471-480
  
• Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti:
  A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. 481-490
  
• Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger:
  A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design. 491-500
  
• Athanasios Kakarountas, Vassilis Spiliotopoulos, Spiridon Nikolaidis, Constantinos E. Goutis:
  The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems. 501-509
  

Low Power (II)

• David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
  Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. 510-520
  
• Gianluca Palermo, Cristina Silvano:
  PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures. 521-531
  
• Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat:
  Power Consumption of Performance-Scaled SIMD Processors. 532-540
  
• Andrea Bona, Vittorio Zaccaria, Roberto Zafalon:
  Low Effort, High Accuracy Network-on-Chip Power Macro Modeling. 541-552
  
• Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu:
  Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. 553-563
  

Low-Power Processing (Poster)

• Ana Rusu, Alexei Borodenkov, Mohammed Ismail, Hannu Tenhunen:
  Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers. 564-573
  
• Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo:
  Power Aware Dividers in FPGA. 574-584
  
• Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan:
  A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. 585-592
  
• Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis:
  The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms. 593-602
  
• Patricia Guitton-Ouhamou, Hanene Ben Fradj, Cécile Belleudy, Spiridon Nikolaidis:
  Low Power Co-design Tool and Power Optimization of Schedules and Memory System. 603-612
  
• Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis:
  Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. 613-622
  
• Sonia López, Oscar Garnica, José Manuel Colmenar:
  Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. 623-632
  
• Nikolaos Kavvadias, Spiridon Nikolaidis:
  Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors. 633-642
  
• Amjad Mohsen, Richard Hofmann:
  Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems. 643-651
  
• Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
  Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. 652-661
  
• Kenny Johansson, Oscar Gustafsson, Lars Wanhammar:
  Power Estimation for Ripple-Carry Adders with Correlated Input Data. 662-674
  
• Mark G. Arnold:
  LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS. 675-684
  

Digital Design (Poster)

• Leonardo Valencia:
  Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits. 685-690
  
• Myeong-Hoon Oh, Dong-Soo Har:
  A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic. 691-700
  
• Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun:
  Pipelines in Dynamic Dual-Rail Circuits. 701-710
  
• Ali Manzak, Chaitali Chakrabarti:
  Optimum Buffer Size for Dynamic Voltage Processors. 711-721
  
• A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne:
  Design Optimization with Automated Cell Generation. 722-731
  
• Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis:
  A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. 732-741
  
• Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis:
  A Novel Constant-Time Fault-Secure Binary Counter. 742-749
  
• Dimitrios Velenis, Eby G. Friedman:
  Buffer Sizing for Crosstalk Induced Delay Uncertainty. 750-759
  
• Panagiotis D. Vouzis, Vassilis Paliouras:
  Optimal Logarithmic Representation in Terms of SNR Behavior. 760-769
  
• Y. S. Son, J. W. Na:
  A New Logic Transformation Method for Both Low Power and High Testability. 770-779
  
• Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow:
  Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. 780-788
  

Modeling and Simulation (Poster)

• Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
  Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. 789-798
  
• Alexander Maili, Damian Dalton, Christian Steger:
  A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. 799-808
  
• Howard Chen, Daniel L. Ostapko:
  Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. 809-818
  
• Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner:
  On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. 819-828
  
• Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa:
  Signal Sampling Based Transition Modeling for Digital Gates Characterization. 829-837
  
• B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
  Physical Extension of the Logical Effort Model. 838-848
  
• Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour, Christer Svensson:
  An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. 849-858
  
• Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
  Moment-Based Estimation of Switching Activity for Correlated Distributions. 859-868
  
• Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson:
  Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. 869-878
  
• Tobias Gemmeke, Tobias G. Noll:
  A Physically Oriented Model to Quantify the Noise-on-Delay Effect. 879-888
  
• Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet:
  Noise Margin in Low Power SRAM Cells. 889-898
  
• Peter Celinski, Derek Abbott, Sorin Cotofana:
  Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. 899-906