18. PATMOS 2008: Lisbon, Portugal

Low-Leakage and Subthreshold Circuits

• Biswajit Mishra, Bashir M. Al-Hashimi:
  Subthreshold FIR Filter Architecture for Ultra Low Power Applications. 1-10
  
• Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
  Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. 11-20
  
• Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici:
  Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. 21-30
  
• Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi:
  Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. 31-41
  

Low-Power Methods and Models

• Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
  Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. 42-51
  
• Roni Wiener, Gila Kamhi, Moshe Y. Vardi:
  Intelligate: Scalable Dynamic Invariant Learning for Power Reduction. 52-61
  
• Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura:
  Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. 62-71
  
• Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed:
  Power-Aware Design via Micro-architectural Link to Implementation. 72-81
  
• Vasily G. Moshnyaga:
  Untraditional Approach to Computer Energy Reduction. 82-92
  

Arithmetic and Memories

• Ioannis Kouretas, Vassilis Paliouras:
  Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. 93-102
  
• Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki:
  Power Optimization of Parallel Multipliers in Systems with Variable Word-Length. 103-115
  
• Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel:
  A Design Space Comparison of 6T and 8T SRAM Core-Cells. 116-125
  
• Yan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel:
  Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization. 126-135
  

Variability and Statistical Timing

• Massimo Alioto, Gaetano Palumbo, Melita Pennisi:
  Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. 136-145
  
• Monica Figueiredo, Rui L. Aguiar:
  A Study on CMOS Time Uncertainty with Technology Scaling. 146-155
  
• Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
  Static Timing Model Extraction for Combinational Circuits. 156-166
  
• Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann:
  A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. 167-177
  
• Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah:
  Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. 178-187
  

Synchronization and Interconnect

• Francisco Fernández-Nogueira, Josep Carmona:
  Logic Synthesis of Handshake Components Using Structural Clustering Techniques. 188-198
  
• Rostislav (Reuven) Dobkin, Ran Ginosar:
  Fast Universal Synchronizers. 199-208
  
• Tsung-Yi Ho:
  A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router. 209-218
  
• Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner:
  PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. 219-228
  

Power Supplies and Switching Noise

• Thomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres:
  Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. 229-236
  
• Giorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco:
  A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint. 237-246
  
• Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luis Miguel Silveira:
  Generating Worst-Case Stimuli for Accurate Power Grid Analysis. 247-257
  
• Nuno Dias, Marcelino B. Santos, Floriberto Lima, Beatriz Borges, Júlio Paisana:
  Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization. 258-267
  

Low-Power Circuits; Reconfigurable Architectures

• Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija:
  Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. 268-276
  
• Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
  A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. 277-286
  
• Maurice Keller, William P. Marnane:
  Energy Efficient Elliptic Curve Processor. 287-296
  
• Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
  Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. 297-306
  
• Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich:
  Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. 307-317
  

Poster Session 1: Circuits and Methods

• Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo:
  Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. 318-327
  
• Omid Mirmotahari, Yngvar Berg:
  Ultra Low Voltage High Speed Differential CMOS Inverter. 328-337
  
• Marco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti:
  Differential Capacitance Analysis. 338-347
  
• Martin Simlastík, Viera Stopjaková:
  Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. 348-358
  
• Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien:
  Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. 359-368
  

Poster Session 2: Power and Delay Modeling

• Ruzica Jevtic, Carlos Carreras:
  Analytical High-Level Power Model for LUT-Based Components. 369-378
  
• Gustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Tavares, Meuse N. Oliveira Jr.:
  A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption. 379-388
  
• Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo:
  Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. 389-398
  
• Felipe Machado, Teresa Riesgo, Yago Torroja:
  Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. 399-408
  
• Francesc Moll, Joan Figueras, Antonio Rubio:
  Data Dependence of Delay Distribution for a Planar Bus. 409-418
  

Power Optimizations Addressing Reconfigurable Architectures

• Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker:
  Towards Novel Approaches in Design Automation for FPGA Power Optimization. 419-428
  
• Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk:
  Smart Enumeration: A Systematic Approach to Exhaustive Search. 429-438
  
• Kostas Siozios, Dimitrios Soudris:
  An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs. 439-448
  
• Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest:
  Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. 449-457
  

Keynotes (Abstracts)

• Floriberto Lima:
  Integration of Power Management Units onto the SoC. 458
  
• Sani R. Nassif:
  Model to Hardware Matching for nm Scale Technologies. 459
  
• Ted Vucurevic:
  Power and Profit: Engineering in the Envelope. 460
  

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