ReConFig 2010: Cancun, Quintana Roo, Mexico

General Sessions

• Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev:
  A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio. 1-6
  
• Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek:
  MARC: A Many-Core Approach to Reconfigurable Computing. 7-12
  
• Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker:
  Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. 13-18
  
• Kaveh Aasaraai, Andreas Moshovos:
  An Efficient Non-blocking Data Cache for Soft Processors. 19-24
  
• Kamana Sigdel, Carlo Galuzzi, Koen Bertels, Mark Thompson, Andy D. Pimentel:
  Runtime Task Mapping Based on Hardware Configuration Reuse. 25-30
  
• Sébastien Guillet, Florent de Lamotte, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet:
  Modeling and Formal Control of Partial Dynamic Reconfiguration. 31-36
  
• Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
  Fault Injection Results of Linux Operating on an FPGA Embedded Platform. 37-42
  
• M. Ashfaquzzaman Khan, Richard Neil Pittman, Alessandro Forin:
  gNOSIS: A Board-Level Debugging and Verification Tool. 43-48
  
• Jochen Strunk, Johannes Hiltscher, Wolfgang Rehm, Heiko Schick:
  Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAs. 49-54
  
• Daniel M. Muñoz, Carlos H. Llanos, Leandro dos Santos Coelho, Mauricio Ayala-Rincón:
  Hardware Particle Swarm Optimization Based on the Attractive-Repulsive Scheme for Embedded Applications. 55-60
  
• Ronald H. Hurtado, Sadek C. A. Alfaro, Carlos Humberto Llanos Quintero:
  FPGA-Based Platform Development for Change Detection in GTAW Welding Process. 61-66
  
• Mariusz Grad, Christian Plessl:
  Pruning the Design Space for Just-in-Time Processor Customization. 67-72
  
• Ouiza Dahmoune, Robert de B. Johnston:
  Applying Model-Checking to Post-Silicon-Verification: Bridging the Specification-Realisation Gap. 73-78
  
• Sascha Mühlbach, Andreas Koch:
  A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. 79-84
  
• Marco A. Moreno-Armendariz, Elsa Rubio, César A. Pérez-Olvera:
  Design and Implementation of a Visual Fuzzy Control in FPGA for the Ball and Plate System. 85-90
  
• Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich:
  Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. 91-96
  
• Daniel Kriesten, Volker Pankalla, Ulrich Heinkel:
  An Application Example of a Run-Time Reconfigurable Embedded System. 97-102
  
• Mingjie Lin, Shaoyi Cheng, John Wawrzynek:
  Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. 103-108
  
• Francisco J. Quiles, Manuel Ortiz, María Brox, Carlos D. Moreno, Javier Hormigo, Julio Villalba:
  UCORE: Reconfigurable Platform for Educational Purposes. 109-114
  
• Azad Fakhari, Mahmood Fathy:
  A Two Level Architecture for High Throughput DCT-Processor and Implementing on FPGA. 115-120
  
• Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
  Parallel FPGA-Based Implementation of Recursive Sorting Algorithms. 121-126
  
• Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni:
  Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart. 127-131
  
• David Pedrosa Branco, Iouliia Skliarova, José Vieira:
  Reconfigurable Digital Audio Mixer for Electroacoustic Music. 132-137
  
• Fadi El-Hassan, Dan Ionescu:
  A Hardware Architecture of an XML/XPath Broker for Content-Based Publish/Subscribe Systems. 138-143
  
• Hamid Mushtaq, Mojtaba Sabeghi, Koen Bertels:
  A Runtime Profiler: Toward Virtualization of Polymorphic Computing Platforms. 144-149
  
• Luis Vitório Cargnini, Yoann Guillemenet, Lionel Torres, Gilles Sassatelli:
  Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM). 150-155
  
• Marco A. Moreno-Armendariz, Nareli Cruz Cortés, Alejandro León-Javier:
  A Novel Hardware Implementation of the Compact Genetic Algorithm. 156-161
  
• Shady O. Agwa, Hany H. Ahmad, Awad I. Saleh:
  Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture. 162-167
  
• J. Pindter-Medina, S. Pichardo, L. Curiel, Andrés David García García, J. E. Chong-Quero:
  Multi-channel Driving Systems for Therapeutic Applications Based-on Focused Ultrasound. 168-172
  
• Luis A. Vera-Salas, Sandra V. Moreno-Tapia, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso:
  Reconfigurable Node Processing Unit for a Low-Power Wireless Sensor Network. 173-178
  
• Bruno A. Silva, Maurício A. Dias, Jorge L. Silva, Fernando Santos Osório:
  Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware. 179-184
  
• Khaled Sobaihi, Akram Hammoudeh, David Scammell:
  FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System. 185-189
  

High Performance Reconfigurable Computing

• Christian de Schryver, Daniel Schmidt, Norbert Wehn, Elke Korn, Henning Marxen, Ralf Korn:
  A New Hardware Efficient Inversion Based Random Number Generator for Non-uniform Distributions. 190-195
  
• Ali Akbar Zarezadeh, Christophe Bobda:
  Performance Analysis of Hardware/Software Middleware in Network of Smart Camera Systems. 196-201
  
• Xiang Tian, Khaled Benkrid:
  Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations. 202-207
  
• Wendi Wang, Bo Duan, Chunming Zhang, Peiheng Zhang, Ninghui Sun:
  Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA. 208-213
  
• Janardhan Singaraju, John A. Chandy:
  Parallel Data Sort Using Networked FPGAs. 214-219
  
• Juan Carlos Díaz Martín, Carolina Gómes-Tostón Gutierrez, Alvaro Cortes Facila, Juan A. Rico-Gallego:
  Issues on Building an MPI Cluster on Microblaze. 220-225
  
• Faisal Nadeem, Mahmood Ahmadi, Muhammad Nadeem, Stephan Wong:
  Modeling and Simulation of Reconfigurable Processors in Grid Networks. 226-231
  
• Ali Reza Akoushideh, Asadollah Shahbahrami:
  Accelerating Texture Features Extraction Algorithms Using FPGA Architecture. 232-237
  
• Marco Antonio Soto Hernandez, Oscar Alvarado Nava, Francisco Javier Zaragoza Martínez:
  Huffman Coding-Based Compression Unit for Embedded Systems. 238-243
  
• Eduardo Cabal-Yepez, Ricardo Saucedo-Gallaga, Armando G. Garcia-Ramirez, Arturo A. Fernandez-Jaramillo, Marcos Pena-Anaya, Martin Valtierra-Rodriguez:
  FPGA-Based Online Detection of Multiple-Combined Faults through Information Entropy and Neural Networks. 244-249
  
• A. D. Santana Gil, Jose Ignacio Benavides Benitez, Manuel Hernandez Calviño, Ezequiel Herruzo Gomez:
  Reconfigurable Cache Implemented on an FPGA. 250-255
  
• Séamas McGettrick, Dermot Geraghty:
  Hardware Computation of the PageRank Eigenvector. 256-261
  

Reconfigurable Computing for Security and Cryptography

• Crina Costea, Florent Bernard, Viktor Fischer, Robert Fouquet:
  Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs. 262-267
  
• Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
  Cross-Correlation Cartography. 268-273
  
• Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang:
  Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs. 274-279
  
• Lubos Gaspar, Viktor Fischer, Florent Bernard, Lilian Bossuet, Pascal Cotret:
  HCrypt: A Novel Concept of Crypto-processor with Secured Key Management. 280-285
  
• Mieczyslaw Jessa, Michal Jaworski:
  High-Speed FPGA-Based Pseudorandom Generators with Extremely Long Periods. 286-291
  
• Aric Schorr, Marcin Lukowiak:
  Skein Tree Hashing on FPGA. 292-297
  
• Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh:
  Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. 298-303
  
• Julien Francq, Céline Thuillet:
  Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results. 304-309
  
• Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne:
  Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA. 310-315
  
• Bernhard Jungk, Steffen Reith:
  On FPGA-Based Implementations of the SHA-3 Candidate Grøstl. 316-321
  
• Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.:
  An Improved GF(2) Matrix Inverter with Linear Time Complexity. 322-327
  

Multiprocessor Systems and Networks on Chip

• Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis:
  Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. 328-333
  
• Andrew G. Schmidt, William V. Kritikos, Ron Sass, Erik K. Anderson, Matthew French:
  Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip. 334-339
  
• Angelo Kuti Lusala, Jean-Didier Legat:
  A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks. 340-345
  
• Nicolas Hebert, Gabriel Marchesan Almeida, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
  A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC. 346-351
  
• Cristinel Ababei:
  Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis. 352-357
  
• Miaoqing Huang, David L. Andrews, Jason Agron:
  Operating System Structures for Multiprocessor Systems on Programmable Chip. 358-363
  
• Rajesh Kannan Megalingam, Ashwin Mohan, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Vivek Periye:
  Low Power Dual Core Microcontroller. 364-369
  
• Ling Liu, Oleksii Morozov:
  A Process-Oriented Streaming System Design Paradigm for FPGAs. 370-375
  
• Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
  R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. 376-381
  
• Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert:
  Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism. 382-387
  
• Sasmita Deo:
  Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform. 388-393
  

Reconfigurable Computing for DSP and Communications

• Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog:
  Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. 394-399
  
• Yue Wang, Kevin Cunningham, Prawat Nagvajara, Jeremy Johnson:
  Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design. 400-405
  
• G. Ramirez-Conejo, Javier Díaz-Carmona, Agustín Ramírez-Agundis, A. Padilla-Medina, J. Delgado-Frias:
  FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters. 406-411
  
• Eduardo Romero-Aguirre, Ramon Parra-Michel, Omar Humberto Longoria-Gandara, M. Aguirre-Hernandez:
  A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPS. 412-417
  

Reconfiguration Techniques

• Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow:
  Using Partial Reconfiguration in an Embedded Message-Passing System. 418-423
  
• Tom Davidson, Karel Bruneel, Dirk Stroobandt:
  Run-Time Reconfiguration for Automatic Hardware/Software Partitioning. 424-429
  
• Piotr Stepien, John Cobb:
  Configuration Sharing Optimized Placment and Routing. 430-435
  
• Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
  Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. 436-441
  

Cyber Physical Systems and Image Processing

• Michael Schmidt, Dietmar Fey:
  An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels. 442-447
  
• Stephen Craven, Daniel Long, Jason Smith:
  Open Source Precision Timed Soft Processor for Cyber Physical System Applications. 448-451
  
• Holger Flatt, Holger Blume, Peter Pirsch:
  Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution. 452-457
  
• Michael Schaeferling, Gundolf Kiefer:
  Flex-SURF: A Flexible Architecture for FPGA-Based Robust Feature Extraction for Optical Tracking Systems. 458-463
  

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