ReCoSoC 2011: Montpellier, France

Special session: Dependability

• Thomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann:
  Invited paper: Design criteria for dependable System-on-Chip architectures. 1-6
  
• Hung-Manh Pham, Ludovic Devaux, Sébastien Pillement:
  Re²DA: Reliable and reconfigurable dynamic architecture. 1-6
  
• Artur Jutman, Sergei Devadze, Igor Aleksejev:
  Invited paper: System-wide fault management based on IEEE P1687 IJTAG. 1-4
  
• Johannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
  Automatic saboteur placement for emulation-based multi-bit fault injection. 1-8
  

Session 1A: Improving communication performance in multicores

• John Shield, Jean-Philippe Diguet, Guy Gogniat:
  Asymmetric cache coherency: Improving multicore performance for non-uniform workloads. 1-8
  
• Tales Marchesan Chaves, Everton Alceu Carara, Fernando Gehm Moraes:
  Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs. 1-6
  
• Leandro Soares Indrusiak:
  Evaluating the feasibility of network coding for NoCs. 1-5
  

Session 1B: Novel techniques and applications of FPGA tool flows

• Ciprian Teodorov, Loïc Lagadec:
  FPGA SDK for nanoscale architectures. 1-8
  
• Ciprian Teodorov, Damien Picard, Loïc Lagadec:
  FPGA physical-design automation using Model-Driven Engineering. 1-6
  

Session 2A: Rapid prototyping of reconfigurable and communication-centric systems

• Damien Picard, Loïc Lagadec:
  Fast prototyping environment for embedded reconfigurable units. 1-8
  
• George Afonso, Rabie Ben Atitallah, Alexander Loyer, Jean-Luc Dekeyser, Nicolas Bélanger, Martial Rubio:
  A prototyping environment for high performance reconfigurable computing. 1-8
  
• Eduardo Wächter, Adelcio Biazi, Fernando Gehm Moraes:
  HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs. 1-8
  

Session 2B: Security issues on reconfigurable systems

• Stephanie Drzevitzky, Marco Platzner:
  Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approach. 1-8
  
• Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Robert Fouquet:
  Secure extensions of FPGA soft core processors for symmetric key cryptography. 1-8
  
• An Braeken, Jan Genoe, Serge Kubera, Nele Mentens, Abdellah Touhafi, Ingrid Verbauwhede, Yannick Verbelen, Jo Vliegen, Karel Wouters:
  Secure remote reconfiguration of an FPGA-based embedded system. 1-6
  

Special session: EU Projects

• Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
  Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach. 1-7
  
• Zoran Stamenkovic, Klaus Tittelbach-Helmrich, Michael Wickert, Jesús Ibáñez, Susana Ruiz, George Dimosthenous:
  Implementation, integration, and verification of MIMAX WLAN modem. 1-8
  
• Kostas Siozios, Dionysios Diamantopoulos, Ioannis Kostavelis, Evangelos Boukas, Lazaros Nalpantidis, Dimitrios Soudris, Antonios Gasteratos, Marcos Avilés, Iraklis Anagnostopoulos:
  SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications. 1-9
  

Tutorial

• Christian Beckhoff, Dirk Koch, Jim Tørresen:
  The Xilinx Design Language (XDL): Tutorial and use cases. 1-8
  

Session 3A: Resource monitoring and management in multiprocessor systems

• Daniela Genius, Nicolas Pouillon:
  Monitoring communication channels on a shared memory multi-processor system on chip. 1-8
  
• Antonios Motakis, George Kornaros, Marcello Coppola:
  Dynamic resource management in modern multicore SoCs by exposing NoC services. 1-7
  
• Nataliya Yakymets, Sébastien Le Beux, Kotb Jabeur, Ian O'Connor:
  Multi-objective mapping for matrix-based nanocomputer architectures. 1-7
  

Session 3B: High-level programming languages for reconfigurable systems

• Laurent Gantel, Amel Khiar, Benoit Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal:
  Dataflow programming model for reconfigurable computing. 1-8
  
• Benjamin Thielmann, Jens Huthmann, Andreas Koch:
  Evaluation of speculative execution techniques for high-level language to hardware compilation. 1-8
  
• Alexandre A. Junqueira, Mateus B. Rutzig, Fábio P. Itturriet, João Victor Portal, Luigi Carro:
  A reconfigurable fabric supporting full C/C++ input. 1-6
  

Session 4A: Advanced on-chip communication

• Cedric Killian, Camel Tanougast, Abbas Dandache, Mohamed Frihi, Salah Toumi:
  A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems. 1-6
  
• Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
  High-performance on-chip network platform for memory-on-processor architectures. 1-6
  
• Taras Iakymchuk, Maciej Nikodem, Krzysztof Kepa:
  Temperature-based covert channel in FPGA systems. 1-7
  

Session 4B: Self reconfigurable systems

• Gian-Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone:
  Partial reconfiguration in the implementation of autonomous radio receivers for space. 1-6
  
• Uros Legat, Anton Biasizzo, Franc Novak:
  Self-reparable system on FPGA for single event upset recovery. 1-6
  
• Salih Bayar, Mehmet Tükel, Arda Yurdakul:
  A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs. 1-9
  

Special session: RCE

• Fearghal Morgan, Seamus Cawley:
  Enhancing learning of digital systems using a remote FPGA lab. 1-8
  
• René Cumplido, Claudia Feregrino Uribe, Jose Juan Garcia-Hernandez:
  Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. 1-6
  

Session 5: Novel routing and flow control techniques for NoCs

• Angelo Kuti Lusala, Jean-Didier Legat:
  A SDM-TDM based circuit-switched router for on-chip networks. 1-8
  
• Daniel Vergeylen, Angelo Kuti Lusala, Jean-Didier Legat:
  A new mechanism to reduce congestion on TDM networks-on-chips. 1-8
  

Session 6: Validating MPSoC designs at multiple levels of abstraction

• Matthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Matthias Krüsselin, Jürgen Becker:
  An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels. 1-8
  
• Luciano Ost, Gabriel Marchesan Almeida, Marcelo Mandelli, Eduardo Wächter, Sameer Varyani, Gilles Sassatelli, Leandro Soares Indrusiak, Michel Robert, Fernando Moraes:
  Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling. 1-8
  

Poster Session PO1

• Laurent Rodriguez, Jérôme Fellus, Benoit Miramond:
  Self-organization of reconfigurable processing elements during mobile robots missions. 1-2
  
• Sven Eisenhardt, Anja Küster, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel:
  Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architectures. 1-2
  
• Emna Amouri, Zied Marrakchi, Habib Mehrez:
  Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. 1-4
  
• Andreas Thuy:
  Comparison of periodic and aperiodic task models for cyber-physical-systems. 1-2
  
• Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere:
  Study and modeling of a new configuration of an optical network on chip (ONOC) using FDTD. 1-2
  
• Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn:
  Towards a power and energy efficient use of partial dynamic reconfiguration. 1-4
  
• Mohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila:
  Exploration of MPSoC monitoring and management systems. 1-3
  
• Gary Plumbridge, Neil C. Audsley:
  Extending Java for heterogeneous embedded system description. 1-6
  
• Oscar Daniel Diaz, Armando Astarloa, Aitzol Zuloaga, Jesús Lázaro, Jaime Jimenez:
  NoCmodel: An extensible framework for Network-on-Chips modeling. 1-6
  

Poster Session PO2

• Sezer Gören, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag:
  FPGA bitstream protection with PUFs, obfuscation, and multi-boot. 1-2
  
• Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
  Efficient congestion-aware selection method for on-chip networks. 1-4
  
• Mahtab Niknahad, Oliver Sander, Jürgen Becker:
  A study on fine granular fault tolerance methodologies for FPGAs. 1-5
  
• Robbe Vancayseele, Brahim Al Farisi, Wim Heirman, Karel Bruneel, Dirk Stroobandt:
  RecoNoC: A reconfigurable network-on-chip. 1-2
  
• Toshinori Takabatake:
  Simulations of NoC topologies for generalized hierarchical completely-connected networks. 1-5
  
• Walid Hassairi, Moncef Bousselmi, Mohamed Abid:
  The co-simulation interface SystemC/Matlab applied in JPEG algorithm. 1-6
  
• Paris Mesidis, Leandro Soares Indrusiak:
  Genetic mapping of hard real-time applications onto NoC-based MPSoCs - A first approach. 1-6
  
• Faizal Arya Samman, Surapong Pongyupinpanich, Manfred Glesner:
  Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems. 1-6
  
• Nadine Dahm, Michael Hübner, Jürgen Becker:
  Approach of an FPGA based adaptive stepper motor control system. 1-6
  

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