11. RSP 2000: Paris, France

Session 1: Co-Design Methodologies

• Marios Iliopoulos, Theodore Antonakopoulos:
  A Methodology for Implementing Medium Access Protocols Using a General Parameterized Architecture. 2-7
  
• Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya:
  Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. 8-13
  
• Johan Cockx:
  Efficient Modeling of Preemption in a Virtual Prototype. 14-19
  
• Randall S. Janka, Linda M. Wills:
  Combining Virtual Benchmarking with Rapid System Prototyping for Real-Time Embedded Multiprocessor Signal Processing System Codesign. 20-
  

Session 2: Software Methodologies

• Juan Carlos Nogueira, Luqi, Swapan Bhattacharya:
  A Risk Assessment Model for Software Prototyping Projects. 28-33
  
• Rajat Moona:
  Processor Models for Retargetable Tools. 34-39
  
• Yolanda González Arechavala, Fernando de Cuadra García:
  MODUS: Integrated Behavior-Oriented Model for Rapid Prototyping. 40-45
  
• Myung-Hwan Park, Ki-Seok Bang, Jin-Young Choi, Inhye Kang:
  Equivalence Checking of Two Statechart Specifications. 46-51
  
• Martin Dimmler, Yves Piguet:
  Intuitive Design of Complex Real-Time Control Systems. 52-
  

Session 3: Tools

• Lovic Gauthier, Ahmed Amine Jerraya:
  Cycle-True Simulation of the ST10 Microcontroller Including the Core and the Peripherals. 60-65
  
• Kenneth B. Kent, Micaela Serra:
  Hardware/Software Co-Design of a Java Virtual Machine. 66-71
  
• Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae:
  Emulator Environment Based on an FPGA Prototyping Board. 72-77
  
• Andreas Koch:
  A Comprehensive Prototyping-Platform for Hardware-Software Codesign. 78-
  

Session 4: Real Time Systems

• Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya:
  Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. 84-89
  
• P. Poure, F. Aubépart, F. Braun:
  A Design Methodology for Hardware Prototyping of Integrated AC Drive Control: Application to Direct Torque Control of an Induction Machine. 90-
  

Session 5: Hardware Methodologies

• N. Cañellas, J. M. Moreno:
  Speeding up Hardware Prototyping by Incremental Simulation/Emulation. 98-102
  
• V. K. Jain:
  Mapping a High-Speed Wireless Communication Function to the Reconfigurable J-Platform. 103-108
  
• Dirk Eilers, Alfred Voglgsang, Arnold Plankl, Gerri Körner, Helmut Steckenbiller, Rudi Knorr:
  A Prototype of an AAL for High Bit Rate Real-Time Data Transmission System over ATM Networks Using a RSE CODEC. 109-114
  
• Wolfram Hardt, Bernd Kleinjohann, Achim Rettberg:
  The FLYSIG Prototyping Approach. 115-
  

Session 6: Code Generation

• David J. Greaves:
  A Verilog to C Compiler. 122-127
  
• Dan Marius Regep, Fabrice Kordon:
  Using MetaScribe to Prototype an UML to C++/Ada95 Code Generator. 128-133
  
• Annette Muth, Thomas Kolloch, Thomas Maier-Komor, Georg Färber:
  An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications. 134-
  

Session 7: Methodologies

• Ansgar Bredenfeld:
  Integration and Evolution of Model-Based Tool Prototypes. 142-147
  
• Romain Kamdem, Alain Fonkoua:
  Coprocessor Synthesis of Multirate System Using Static Scheduling Theory. 148-153
  
• Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
  Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. 154-159
  
• Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner:
  Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. 160-
  

Session 8: Reconfigurability in Hardware Systems

• Francisco Barat, Rudy Lauwereins:
  Reconfigurable Instruction Set Processors: A Survey. 168-173
  
• Eduardo de la Torre, Teresa Riesgo, J. Uceda, E. Macip, M. Rizzi:
  Highly Configurable Control Boards: A Tool and a Design Experience. 174-
  

Session 9: Hardware Systems

• Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
  Power-Constrained Block-Test List Scheduling. 182-187
  
• Juan de Vicente, Juan Lanchares, Román Hermida:
  Adaptive FPGA Placement by Natural Optimization. 188-193
  
• Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man:
  A Hardware Virtual Machine for the Networked Reconfiguration. 194-199
  
• Helena Krupnova, Gabriele Saucier:
  FPGA Technology Snapshot: Current Devices and Design Tools. 200-
  

Session 10: Industrial Session

Session 11: Methodologies

• P. G. Prasad:
  Validation of Link Layer Synthesizable Core - A Prototyping Case Study. 208-213
  
• Ulrich Mayer, Manfred Glesner:
  Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams. 214-
  

Session 12: Embedded Systems

• Göran Eggers, Hans Christoph Zeidler:
  Efficient Clock-Cycle Precise Simulation at Architecture Level in C++. 222-
  
• Carsten Nitsch, Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel:
  Embedded System Architecture Design Based on Real-Time Emulation. 228-233
  

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