21. RSP 2010: Fairfax, VA, USA
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, RSP 2010, Fairfax, VA, USA, 8-11 June, 2010. IEEE Computer Society 2010 ISBN 978-1-4244-7073-0- Doron Drusinsky, Man-tak Shing: Validating quality attribute requirements via execution-based model checking. 1-7
- Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin: Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip. 1-9
- Walid Lafi, Didier Lattard, Ahmed Amine Jerraya: An efficient hierarchical router for large 3D NoCs. 1-5
- Hsiang-Huang Wu, Hojin Kee, Nimish Sane, William Plishker, Shuvra S. Bhattacharyya: Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs. 1-7
- Martin Hillenbrand, Matthias Heinz, Nico Adler, Johannes Matheis, Klaus D. Müller-Glaser: Failure mode and effect analysis based on electric and electronic architectures of vehicles to support the safety lifecycle ISO/DIS 26262. 1-7
- Marco Lattuada, Fabrizio Ferrandi: Fine grain analysis of simulators accuracy for calibrating performance models. 1-7
- Gavin Xiaoxu Yao, Ray C. C. Cheung, Kim Fung Man: Counter Embedded Memory architecture for trusted computing platform. 1-7
- Zulfiqar Ali, Ali Arshad, Umair Razzaq: An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing. 1-7
- Ananya Kanjilal, Sabnam Sengupta, Swapan Bhattacharya: Scenario path identification for distributed systems: A graph based approach. 1-8
- Youcef Bouchebaba, Pierre G. Paulin, Ali Erdem Özcan, Bruno Lavigueur, Michel Langevin, Olivier Benny, Gabriela Nicolescu: MpAssign: A framework for solving the many-core platform mapping problem. 1-7
- Graham Hemingway, Joseph Porter, Nicholas Kottenstette, Harmon Nine, Christopher P. van Buskirk, Gabor Karsai, Janos Sztipanovits: Automated synthesis of Time-Triggered Architecture-based TrueTime models for platform effects simulation and analysis. 1-7
- Ronaldo Husemann, Mariano Majolo, Valter Roesler, José Valdeni de Lima, Altamiro Amadeu Susin: Highly efficient forward two-dimensional DCT module architecture for H.264/SVC. 1-7
- Andrew Forward, Omar Bahy Badreddin, Timothy C. Lethbridge: Umple: Towards combining model driven with prototype driven system development. 1-7
- Atef Allam, Ian O'Connor, W. Heirman: Performance evaluation for passive-type Optical network-on-chip. 1-7
- Martin Hillenbrand, Matthias Heinz, Klaus D. Müller-Glaser, Nico Adler, Johannes Matheis, Clemens Reichmann: An approach for rapidly adapting the demands of ISO/DIS 26262 to electric/electronic architecture modeling. 1-7
- Martin Hillenbrand, Matthias Heinz, Klaus D. Müller-Glaser: Rapid specification of hardware-in-the-loop test systems in the automotive domain based on the electric / electronic architecture description of, vehicles. 1-6
- Trang T. T. Do, Thinh M. Le, Binh P. Nguyen, Yajun Ha: Performance-cost analyses software for H.264 Forward/Inverse Integer Transform. 1-7
- Samar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski: Embedded system environment: A framework for TLM-based design and prototyping. 1-7
- Gunar Schirner: Exploring SW performance using preemptive RTOS models. 1-7
- Andreas Gerstlauer: Host-compiled simulation of multi-core platforms. 1-6
- Andreas Gerstlauer: Host-compiled simulation of multi-core platforms. 1-6
- Adolfo Recio, Jorge Alberto Surís, Peter Athanas: Automatic modulation classification for rapid radio deployment. 1-7
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last updated on 2013-06-18T211851 by the dblp team