ICSAMOS 2006: Samos, Greece

Embedded Processors and Architectures

• Eero Aho, Jarno Vanne, Timo D. Hämäläinen:
  Parallel Memory Implementation for Arbitrary Stride Accesses. 1-6
  
• Shaahin Hessabi, Mehdi Modarressi, Maziar Goudarzi, Hani JavanHemmat:
  A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. 7-13
  
• Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
  On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. 14-20
  
• Francisco J. Villa, Manuel E. Acacio, José M. García:
  On the Evaluation of Dense Chip-Multiprocessor Architectures. 21-27
  

Energy Aware Processors

• Md. Mafijul Islam, Per Stenström:
  Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. 28-34
  
• Kashif Ali, Mokhtar Aboelaze, Suprakash Datta:
  Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors. 35-42
  
• Sébastien Lafond, Johan Lilius:
  Static Energy Saving Through Multi-Bank Memory Architecture. 43-49
  
• Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris:
  Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors. 50-55
  

Design Space Exploration I

• Hartwig Jeschke:
  Design Space Expoloration Chip Size Estimation for SOC Design Space Exploration. 56-62
  
• Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal:
  Profiling Driven Scenarion Detection and Prediction for Multimedia Applications. 63-70
  
• Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas:
  On the Calibration of Abstract Performance Models for System-level Design Space Exploration. 71-77
  
• Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal:
  Pareto-Based Application Specification for MP-SoC Customized Run-Time Management. 78-84
  

Design Space Exploration II

• Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis:
  Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path. 85-92
  
• Thilo Streichert, Christian Haubelt, Jürgen Teich:
  Multi-Objective Topology Optimization for Networked Embedded Systems. 93-98
  
• Rainer Schaffer, Renate Merker:
  Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. 99-106
  
• Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo:
  Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. 107-114
  

High Level System Design and Simulation

• Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
  An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. 115-122
  
• Hannes Muhr, Roland Höler:
  Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression. 123-127
  
• Selim Gurun, Ye Wen, Navraj Chohan, Richard Wolski, Chandra Krintz:
  SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node. 129-136
  
• Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya:
  Memory-constrained Block Processing Optimization for Synthesis of DSP Software. 137-143
  

System and NoC Platforms

• Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
  Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. 144-151
  
• Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf:
  Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. 152-159
  
• Stamatis Vassiliadis, Ioannis Sourdis:
  FLUX Networks: Interconnects on Demand. 160-167
  

Reconfigurable Processors and Applications of ES

• N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
  On-Chip Communication in Run-Time Assembled Reconfigurable Systems. 168-176
  
• Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk:
  Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. 177-184
  
• Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven:
  Throughput optimization via cache partitioning for embedded multiprocessors. 185-192
  

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