ICSAMOS 2007: Samos, Greece
Holger Blume, Georgi Gaydadjiev, C. John Glossner, Peter M. W. Knijnenburg (Eds.): Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007. IEEE 2007 ISBN 1-4244-1058-4
Processor Architectures
- Peter Westermann, Ludwig Schwoerer, Andre Kaufmann: Applying Data Mapping Techniques to Vector DSPs. 1-8
- Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. 18-25
- Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis G. Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis: Prototyping Efficient Interprocessor Communication Mechanisms. 26-33
Design Space Exploration
- Christoforos Kachris, Stamatis Vassiliadis: Design Space Exploration of Configuration Manager for Network Processing Applications. 34-40
- Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch: Design Space Exploration of Media Processors: A Parameterized Scheduler. 41-49
- Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi: Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. 50-57
- Lazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris: Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems. 58-65
Multiprocessor Architectures
- Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero: On the Problem of Minimizing Workload Execution Time in SMT Processors. 66-73
- Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek: Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. 74-81
- Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto: An Interrupt Controller for FPGA-based Multiprocessors. 82-87
- Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert: Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems. 88-95
Systems and Applications
- Sergio A. Cuenca, Antonio Martinez, Antonio Jimeno, José Luis Sánchez: A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining. 96-102
- Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis: Instruction-Level Fault Tolerance Configurability. 110-117
- Benoît Garbinato, Rachid Guerraoui, Jarle Hulaas, Alexei Kounine, Maxime Monod, Jesper Honig Spring: The Weight-Watcher Service and its Lightweight Implementation. 118-127
Reconfigurable Architectures
- Kehuai Wu, Jan Madsen: COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems. 128-136
- Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. 137-144
- Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo: An Evolutionary Approach to Area-Time Optimization of FPGA designs. 145-152
- Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis: The ARISE Reconfigurable Instruction Set Extensions Framework. 153-160
Memory Architectures and Memory Optimization
- Joachim Keinert, Christian Haubelt, Jürgen Teich: Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. 161-168
- Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Online Prediction of Applications Cache Utility. 169-177
- Ezequiel Herruzo, Emilio L. Zapata, Oscar G. Plata: Maximum and Sorted Cache Occupation Using Array Padding. 178-185
- Vassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos: A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems. 186-193
Cryptography
- Nele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede: A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications. 194-200
- Sascha Mühlbach, Sebastian Wallner: Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines. 201-208
- Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. 209-214
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last updated on 2013-06-19T203413 by the dblp team