SAMOS 2009: Samos, Greece

Beachnote

• Yale N. Patt:
  What Else Is Broken? Can We Fix It? 1
  

Architectures for Multimedia

• Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala:
  Programmable and Scalable Architecture for Graphics Processing Units. 2-11
  
• Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé:
  The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. 12-23
  
• Yahya Jan, Lech Józwiak:
  CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. 24-35
  
• Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén:
  Programmable Accelerators for Reconfigurable Video Decoder. 36-47
  
• Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor:
  Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study. 48-57
  
• Roya Choupani, Stephan Wong, Mehmet R. Tolun:
  Multiple Description Scalable Coding for Video Transmission over Unreliable Networks. 58-67
  

Multi/Many Cores Architectures

• Sascha Uhrig:
  Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC. 68-77
  
• Roberto Giorgi, Zdravko Popovic, Nikola Puzovic:
  Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. 78-87
  
• Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi:
  Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. 88-97
  
• Christian Schäck, Wolfgang Heenes, Rolf Hoffmann:
  A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA. 98-107
  

VLSI Architectures Design

• Nainesh Agarwal, Nikitas J. Dimopoulos:
  Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. 108-117
  
• Ismo Hänninen, Jarmo Takala:
  Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata. 118-127
  
• Ying Xu, Aabhas S. Agarwal, Brian T. Davis:
  Prediction in Dynamic SDRAM Controller Policies. 128-138
  
• Shinichi Kato, Minoru Watanabe:
  Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. 139-148
  

Architecture Modeling and Exploration Tools

• Toktam Taghavi, Mark Thompson, Andy D. Pimentel:
  Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration. 149-160
  
• Peter Westermann, Hartmut Schröder:
  Modeling Scalable SIMD DSPs in LISA. 161-170
  
• Per Karlström, Dake Liu:
  NoGAP: A Micro Architecture Construction Framework. 171-180
  
• Bernhard Huber, Roman Obermaisser:
  A Comparison of NoTA and GENESYS. 181-192
  

Special Session 1: Instruction-Set Customization

• Carlo Galuzzi:
  Introduction to Instruction-Set Customization. 193
  
• Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot:
  Constraint-Driven Identification of Application Specific Instructions in the DURASE System. 194-203
  
• Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
  A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). 204-214
  
• Huynh Phung Huynh, Tulika Mitra:
  Runtime Adaptive Extensible Embedded Processors - A Survey. 215-225
  

Special Session 2: The Future of Reconfigurable Computing and Processor Architectures

• Luigi Carro, Stephan Wong:
  Introduction to the Future of Reconfigurable Computing and Processor Architectures. 226
  
• Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl:
  An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems. 227-236
  
• Frederico Pratas, Leonel Sousa:
  Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study. 237-246
  
• Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge:
  Reconfigurable Multicore Server Processors for Low Power Operation. 247-254
  
• Walid A. Najjar, Jason R. Villarreal:
  Reconfigurable Computing in the New Age of Parallelism. 255-262
  
• Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev:
  Reconfigurable Multithreading Architectures: A Survey. 263-274
  

Special Session 3: Mastering Cell BE and GPU Execution Platforms

• Ed F. Deprettere, Ana Lucia Varbanescu:
  Introduction to Mastering Cell BE and GPU Execution Platforms. 275-276
  
• Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich:
  Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. 277-288
  
• Alexander Monakov, Arutyun Avetisyan:
  Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs. 289-297
  
• Sander van der Maar, Kees Joost Batenburg, Jan Sijbers:
  Experiences with Cell-BE and GPU for Tomography. 298-307
  
• Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere:
  Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell. 308-317
  
• Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta:
  Exploiting Locality on the Cell/B.E. through Bypassing. 318-328
  
• Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis:
  Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System. 329-339
  

Last update Tue May 21 00:05:11 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page