SBAC-PAD 2004:
Foz do Iguacu, Brazil
16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil.
IEEE Computer Society 2004, ISBN 0-7695-2240-8
Cache and Memory Architectures
- Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt:
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance.
2-9

- Yue Luo, Lizy Kurian John, Lieven Eeckhout:
Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation.
10-17

- Martin Ohmacht, Dirk Hoenicke, Ruud A. Haring, Alan Gara:
The eDRAM based L3-Cache of the BlueGene/L Supercomputer Processor Node.
18-22

- Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo:
Multi-Profile Instruction Based Compression.
23-29

Processor Architectures I
Processor Architectures II
Languages and Tools for Parallel and Distributed Programming
Grid, Cluster and Pervasive
- Sébastien Varrette, Jean-Louis Roch, Franck Leprévost:
FlowCert : Probabilistic Certification for Peer-to-Peer Computations.
108-115

- Jean-Michel Busca, Marin Bertier, Fatima Belkouch, Pierre Sens, Luciana Bezerra Arantes:
A Performance Evaluation of a Quorum-Based State-Machine Replication Algorithm For Computing Grids.
116-123

- Walfredo Cirne, Francisco Vilar Brasileiro, Lauro Costa, Daniel Paranhos da Silva, Elizeu Santos-Neto, Nazareno Andrade, César A. F. De Rose, Tiago C. Ferreto, Miranda Mowbray, Roque Scheer, João Jornada:
Scheduling in Bag-of-Task Grids: The PAUÁ Case.
124-131

- Albano Alves, António Pina, José Exposto, José Rufino:
memu: Unifying Application Modeling and Cluster Exploitation.
132-139

High Performance Applications
Parallel and Distributed Algorithms
Load Balancing and Scheduling
Benchmarking, Performance Measurements and Analysis
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