SiPS 2009: Tampere, Finland

DSP for Communications I

• Renfei Liu, Keshab K. Parhi:
  Sparse severe error removal in OFDM demodulators for erasure channels. 001-006
  
• Clemens Buchacher, Joachim Wehinger, Mario Huemer:
  A novel circulant approximation method for frequency domain LMMSE equalization. 007-012
  
• Jang Woong Park, Myung Hoon Sunwoo, Pansoo Kim, Dae-Ig Chang:
  Multi-level modulation soft-decision demapper for DVB-S2. 013-017
  
• Meng Li, Charbel Abdel Nour, Christophe Jégo, Catherine Douillard:
  Design of rotated QAM mapper/demapper for the DVB-T2 standard. 018-023
  

DSP for Communications II

• Praveen Raghavan, Francky Catthoor:
  Register file exploration for a multi-standard wireless forward error correction ASIP. 024-029
  
• Fabio Garzia, Roberto Airoldi, Tapani Ahonen, Jari Nurmi, Dragomir Milojevic:
  Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios. 030-035
  
• Sangho Yoon, Hanho Lee, Kihoon Lee, Chang-Seok Choi, Jongyoon Shin, Jongho Kim, Je-Soo Ko:
  Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications. 036-039
  
• Junho Cho, Naresh R. Shanbhag, Wonyong Sung:
  Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. 040-045
  

Posters I

• Meng-Lin Hsia, Chih-Feng Tseng, Meng-Hsuan Chan, Oscal T.-C. Chen:
  Low-complexity frame-size down-scaling integrated with IDCT. 046-050
  
• Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh:
  Is the differential frequency-based attack effective against random delay insertion? 051-056
  
• Claudio Brunelli, Heikki Berg, David Guevorkian:
  Approximating sine functions using variable-precision Taylor polynomials. 057-062
  
• Vladimír Guzma, Teemu Pitkänen, Pertti Kellomäki, Jarmo Takala:
  Reducing processor energy consumption by compiler optimization. 063-068
  
• Amit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi:
  Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry. 069-074
  
• Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu:
  Parallel object detection on multicore platforms. 075-080
  
• Lassi Nurmi, Perttu Salmela, Pertti Kellomäki, Pekka Jääskeläinen, Jarmo Takala:
  Reconfigurable video decoder with transform acceleration. 081-086
  
• Jae-Woo Ahn, Hoseok Chang, Junho Cho, Wonyong Sung:
  SIMD processor based implementation of recursive filtering equations. 087-092
  

Video Processing

• Kangjun Lee, Gwanggil Jeon, Rafael Falcón, Changwoo Ha, Jechang Jeong:
  An adaptive fast multiple reference frame selection algorithm for H.264/AVC using reference region data. 093-096
  
• Jungho Do, Sangkwon Na, Chong-Min Kyung:
  An early block type decision method for intra prediction in H.264/AVC. 097-101
  
• Guilherme Corrêa, Thaísa Leal da Silva, Luís A. Cruz, Luciano Volcan Agostini:
  Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering order. 102-108
  
• Young-Joon Jo, Jin-Su Jung, Hyuk-Jae Lee:
  Fast pipeline schedule for an H.264 intra frame encoder with early termination. 109-114
  

DSP Implementations I

• Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
  Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. 115-120
  
• Jungsub Kim, Chi-Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti:
  FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data. 121-126
  
• Ning Chen, Maximilien Gadouleau, Zhiyuan Yan:
  Rank metric decoder architectures for noncoherent error control in random network coding. 127-132
  

Design Methods and Tools

• Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy:
  System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning. 133-138
  
• Meng Wang, Duo Liu, Yi Wang, Zili Shao:
  Loop scheduling with memory access reduction under register constraints for DSP applications. 139-144
  
• Jonathan Piat, Shuvra S. Bhattacharyya, Mickaël Raulet:
  Interface-based hierarchy for synchronous data-flow graphs. 145-150
  
• David Novo, Robert Fasthuber, Praveen Raghavan, André Bourdoux, Min Li, Liesbet Van der Perre, Francky Catthoor:
  Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. 151-156
  

DSP Implementations II

• Sung Gug Kim, Yoo Shin Kim, Il Kyu Eom:
  Locally adaptive speckle noise reduction using maximum a posteriori estimation based on Maxwell distribution. 157-160
  
• Teemu Laukkarinen, Ville Kaseva, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen:
  HybridKernel: Preemptive kernel with event-driven extension for resource constrained wireless sensor networks. 161-166
  
• Muhammad Ali Shami, Ahmed Hemani:
  Morphable DPU: Smart and efficient data path for signal processing applications. 167-172
  
• Daewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo-Ik Chae:
  Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks. 173-178
  

Posters II

• Bo Yuan, Li Li, Zhongfeng Wang:
  High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications. 179-184
  
• Rami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag:
  Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. 185-190
  
• Xuebin Wu, Zhiyuan Yan:
  CAC CODEC designs based on numeral systems. 191-196
  
• Ville Kaseva, Timo D. Hämäläinen, Marko Hännikäinen:
  Robust tree construction and maintenance for global time synchronization protocols in Wireless Sensor Networks. 197-201
  
• Asgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour:
  A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS. 202-207
  
• Juuso Alhava, Markku Renfors:
  Rectangular constellation-based blind equalization with recursive least-squares algorithm. 208-213
  
• Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
  An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. 214-219
  

DSP for Communications III

• Cédric Marchand, Jean-Baptiste Dore, Laura Conde-Canencia, Emmanuel Boutillon:
  Conflict resolution for pipelined layered LDPC decoders. 220-225
  
• Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu:
  A Channel-Adaptive Early Termination strategy for LDPC decoders. 226-231
  
• Kevin Cushon, Warren J. Gross, Shie Mannor:
  Bidirectional interleavers for LDPC decoders using transmission gates. 232-237
  
• Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
  An improved min-sum based column-layered decoding algorithm for LDPC codes. 238-242
  

Image Processing

• Minsoo Rhu, In-Cheol Park:
  A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. 243-248
  
• Davide Anastasia, Yiannis Andreopoulos:
  Software designs of image processing tasks with incremental refinement of computation. 249-254
  
• Eero Aho, Kimmo Kuusilinna, Jari Nikara:
  Memory access characteristics of H.264 video encoder on embedded processor. 255-260
  

Special Session: DSP in GNSS

• Heikki Hurskainen, Elena Simona Lohan, Jari Nurmi, Stephan Sand, Christian Mensing, Marco Detratti:
  Optimal dual frequency combination for Galileo mass market receiver baseband. 261-266
  
• Antonio Cavaleri, Letizia Lo Presti, Marco Pini:
  Enhancing GNSS signal acquisition through the Gradient method. 267-272
  
• Martti Kirkko-Jaakkola, Johannes Traugott, Dennis Odijk, Jussi Collin, Gottfried Sachs, Florian Holzapfel:
  A RAIM approach to GNSS outlier and cycle slip detection using L1 carrier phase time-differences. 273-278
  

Special Session: DSP on GPUs

• Jyrki Leskela, Jarmo Nikula, Mika Salmela:
  OpenCL embedded profile prototype in mobile device. 279-284
  
• Hyunwoo Ji, Junho Cho, Wonyong Sung:
  Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit. 285-290
  

Special Session: DSP on GPUs

• Svetislav Momcilovic, Leonel Sousa:
  Development and evaluation of scalable video motion estimators on GPU. 291-296
  
• Shang-Te Yang, Tsung-Kai Lin, Shao-Yi Chien:
  Real-time Motion Estimation for 1080p videos on graphics processing units with shared memory optimization. 297-302
  
• Michael Wu, Siddharth Gupta, Yang Sun, Joseph R. Cavallaro:
  A GPU implementation of a real-time MIMO detector. 303-308
  
• Carmine Clemente, Maurizio di Bisceglie, Michele Di Santo, Nadia Ranaldo, Marcello Spinelli:
  Processing of synthetic Aperture Radar data with GPGPU. 309-314
  

Last update Sat May 18 19:47:07 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page