7. SLIP 2005:
San Francisco,
CA,
USA
Igor L. Markov, Mike Hutton (Eds.):
The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings.
ACM 2005, ISBN 1-59593-033-7
Interconnect scaling
- Ron Ho:
High-performance ULSI: the real limiter to interconnect scaling.
3
Interconnect optimization
- Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu:
Prediction of delay time for future LSI using on-chip transmission line interconnects.
7-12
- Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi:
Predictions of CMOS compatible on-chip optical interconnect.
13-20
- J. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
Package level interconnect options.
21-27
- Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen:
Multilevel full-chip routing with testability and yield enhancement.
29-36
Interconnect variation
Interconnect prediction
Power and noise
- David J. Hathaway:
Dealing with the spatio-temporal interactions among transient power, supply noise and timing.
61
Interconnect in three dimensions
Design issues for interconnect
- Jens Lienig:
Interconnect and current density stress: an introduction to electromigration-aware design.
81-88
nterconnect congestion estimation
Copyright © Sun Nov 15 03:06:38 2009
by Michael Ley (ley@uni-trier.de)