8. SLIP 2006: Munich, Germany

Prediction of individual wire properties

• Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
  Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. 3-8
  
• Pranav Anbalagan, Jeffrey A. Davis:
  A priori prediction of tightly clustered connections based on heuristic classification trees. 9-15
  
• Andrew B. Kahng, Sherief Reda:
  A tale of two nets: studies of wirelength progression in physical design. 17-24
  

Process variation

• Louis Scheffer:
  An overview of on-chip interconnect variation. 27-28
  
• Andrew B. Kahng, Rasit Onur Topaloglu:
  Generation of design guarantees for interconnect matching. 29-34
  

Design for manufacturability

• Chandu Visweswariah:
  Statistical analysis and optimization in the presence of gate and interconnect delay variations. 37
  

Evaluation and prediction of FPGA routing resources

• Wenyi Feng, Jonathan W. Greene:
  Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? 41-48
  
• Manuel Saldaña, Lesley Shannon, Paul Chow:
  The routability of multiprocessor network topologies in FPGAs. 49-56
  

Prediction and Optimization of global interconnect architectures

• Wim Heirman, Joni Dambre, Jan M. Van Campenhout:
  Congestion modeling for reconfigurable inter-processor networks. 59-66
  
• Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho:
  Modeling and analysis of the system bus latency on the SoC platform. 67-74
  
• Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor:
  Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. 75-81
  

Physical interconnect analysis and optimization

• Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex:
  Impact of interconnect resistance increase on system performance of low power and high performance designs. 85-90
  
• Andrew B. Kahng, Bao Liu, Xu Xu:
  Statistical crosstalk aggressor alignment aware interconnect delay calculation. 91-97
  
• J. Balachandran, Steven Brebels, G. Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
  Constant impedance scaling paradigm for interconnect synthesis. 99-105
  

Optimal interconnect buffering

• Prashant Saxena:
  The scaling of interconnect buffer needs. 109-112
  
• Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
  Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. 113-120