SoCC 2007: Tampere, Finland

• Hwei-Yu Lee, Shen-Iuan Liu:
  A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology. 3-6
  
• Kilhwan Kim, Unsun Cho, Seunghyun Lim, Youngcheol Chae, Yunho Jung, Gunhee Han, Jaeseok Kim:
  A 1.5V mixed signal biomedical SOC for implantable cardioverter defibrillators. 7-10
  
• Hwei-Yu Lee, I.-Hsin Wang, Shen-Iuan Liu:
  A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS. 11-14
  
• Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, Chung-Chih Hung:
  A 1V CMOS low-noise amplifier with inductive resonated for 3.1-10.6GHz UWB wireless receiver. 15-18
  
• Chung-Jr Lian, Po-Chih Tseng, Tung-Chien Chen, Yu-Wei Chang, Liang-Gee Chen:
  Reconfigurable architecture for video applications. 21-24
  
• Sanu Mathew, David Harris, Mark Anders, Steven Hsu, Ram Krishnamurthy:
  A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS. 25-28
  
• Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey:
  Design of cost-efficient memory-based FFT processors using single-port memories. 29-32
  
• Chu Yu, Hwai-Tsu Hu:
  A compact pipelined architecture with high-throughput for context-based binary arithmetic coding. 33-36
  
• Andrew Marshall, C. Rinn Cleavelin, Weize Xiong, Christian Pacha, Gerhard Knoblinger, Klaus Von Armin, Thomas Schulz, Klaus Schruefer, Ken Matthews, Wolfgang Molzer, Paul Patruno, Christian Russ:
  A merged MuGFET and planar SOI process. 39-42
  
• Yuh-Shyan Hwang, Jeen-Fong Lin, Cheng-Chung Huang, Jiann-Jong Chen, Wen-Ta Lee:
  An efficient power reduction technique for flash ADC. 43-46
  
• Tsung-Sum Lee, Chi-Chang Lu, Jian-Ting Zhan:
  A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit. 47-50
  
• Guang-Huei Lin, Ya-Nan Wen, Xiao-Long Wu, Sao-Jie Chen, Yu Hen Hu:
  Design of a SIMD multimedia SoC platform. 51-54
  
• Liang Lu, John V. McCanny, Sakir Sezer:
  Reconfigurable video motion estimation processor. 55-58
  
• Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan:
  Reduced computation and memory access for VBSME using pixel truncation. 59-62
  
• Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun:
  An independent-gate FinFET SRAM cell for high data stability and enhanced integration density. 63-66
  
• Won-Jin Kim, Ki-Seok Chung:
  An incremental floorplanning algorithm for temperature reduction. 67-70
  
• Jeong Hun Kim, Jeongwoo Park, Kwangjae Lee, Kyoungbum Kim, Kwang-Hyun Baek, Suki Kim:
  Surveillance camera SOC architecture using one-bit motion detection for portable applications. 71-74
  
• Minoru Watanabe:
  An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. 75-78
  
• Manjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar:
  Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level. 79-82
  
• Jun Mu, Sakir Sezer, Gareth Douglas, Dwayne Burns, Emi Garcia, Mike Hutton, Kevin Cackovic:
  Accelerating pattern matching for DPI. 83-86
  
• Sinae Ji, Woon Hong Kim, Chulho Chung, Jaeseok Kim:
  A ZigBee compliant baseband and MAC processor. 87-90
  
• Varun V. Ramaswamy, Manjari Agarwal, Ramalingam Sridhar:
  Robust 3GHz CMOS low noise amplifier adapted for RFID receivers. 91-94
  
• Costas Argyrides, Dhiraj K. Pradhan:
  Improved decoding algorithm for high reliable reed muller coding. 95-98
  
• Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, Chung-Chih Hung:
  A 1V-2.39mW capacitor-coupling resonated low noise amplifier for 3-5GHz ultra-wideband system. 101-104
  
• Minglang Lin, Ahmet T. Erdogan, Tughrul Arslan, Adrian Stoica:
  A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector. 105-108
  
• Mingzhen Wang, Chien-In Henry Chen:
  Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications. 109-112
  
• Yuan Sun, Liter Siek:
  A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC. 113-116
  
• Costas Argyrides, Ahmad A. Al-Yamani, Dhiraj K. Pradhan:
  High defect tolerant low cost memory chips. 119-122
  
• Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu:
  Programmable CRC circuit architecture. 123-126
  
• Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, Kiyoung Choi:
  Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture. 127-130
  
• Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan, Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi:
  Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture. 131-134
  
• Amirali Shayan Arani:
  Online thermal-aware scheduling for multiple clock domain CMPs. 137-140
  
• Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu:
  Design of ultra low power CML MUXs and latches with forward body bias. 141-144
  
• Sherif A. Tawfik, Volkan Kursun:
  Low-power high-performance FinFET sequential circuits. 145-148
  
• Sumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda:
  H.264/AVC decoder SoC towards the low cost mobile video player. 151-154
  
• Junghee Lee, Joonhwan Yi:
  Industrial experience with cycle error computation of cycle-accurate transaction level models. 155-158
  
• Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan:
  Power evaluation of the arbitration policy for different on-chip bus based SoC platform. 159-162
  
• Kaijian Shi, Jingsong Li:
  A wakeup rush current and charge-up time analysis method for programmable power-gating designs. 163-165
  
• Youse Kim, Naeun Zang, Juho Kim:
  Stochastic glitch elimination considering path correlation. 169-172
  
• Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan:
  Power estimation framework for single processor based SoC platform. 173-176
  
• Hou-Ming Chen, Robert C. Chang, Chih-Liang Huang:
  Low-voltage zero quiescent current PFM boost converter for portable devices. 177-180
  
• Jiun-Yi Lin, Li-Rong Wang, Chia-Lin Hu, Shyh-Jye Jou:
  Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. 181-184
  
• Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
  Early selection of system implementation choice among SoC, SoP and 3-D Integration. 187-190
  
• Tiberiu Seceleanu, Ville Leppänen, Olli Nevalainen:
  Device allocation on the SegBus platform based on communication scheduling cost minimization. 191-196
  
• Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser:
  Multilevel MPSOC simulation using an MDE approach. 197-200
  
• Chun-Jen Wei, Guang-Huei Lin, Ya-Nan Wen, Sao-Jie Chen, Yu Hen Hu:
  Symbolic verification and error prediction methodology. 201-204
  
• Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
  A 65nm low power 2T1D embedded DRAM with leakage current reduction. 207-210
  
• D. P. Wang, H. J. Liao, H. Yamauchi, Y. H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, H. C. Chang, W. Hwang:
  A 45nm dual-port SRAM with write and read capability enhancement at low voltage. 211-214
  
• Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
  A versatile content addressable memory architecture. 215-218
  
• Chang-Hsuan Chang, Ming-Hung Chang, Wei Hwang:
  A flexible two-layer external memory management for H.264/AVC decoder. 219-222
  
• Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang:
  A prototype of a wireless-based test system. 225-228
  
• ChenFeng Chang, YaoWen Chang:
  X-Route: An X-architecture full-chip multilevel router. 229-232
  
• Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu:
  Using power gating techniques in area-array SoC floorplan design. 233-236
  
• Hsing-Chih Hung, Ting-Hao Lin, Chung-Yang Huang:
  QuteIP: An IP qualification framework for System on Chip. 237-240
  
• Wei-Cheng Lin, Chung-Ho Chen:
  A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder. 243-246
  
• Cihun-Siyong Alex Gong, Muh-Tian Shiue, Ci-Tong Hong, Chun-Hsien Su, Kai-Wen Yao:
  Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications. 247-250
  
• Xiaolin Chen, Nishan Canagarajah, Jose Luis Nunez-Yanez, Raffaele Vitulli:
  Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding. 251-254
  
• Vijayavardhan Baireddy, Himamshu Khasnis, Rajesh Mundhada:
  A programmable FFT/IFFT/Windowing processor for multi standard DSL applications. 255-258
  
• Darsun Tsiena, Chien Kuo Wang, William W. J. Wang, Yajun Ran, Philippe Hurat, Nishath Verghese:
  Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability. 261-268
  
• Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari:
  Assertion based design error diagnosis for core-based SoCs. 269-272
  
• Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng:
  Diagnosing scan chains using SAT-based diagnostic pattern generation. 273-276
  
• Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng:
  ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. 277-280
  
• Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee:
  Hierarchical power delivery network analysis using Markov chains. 283-286
  
• I. Hatyrnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici:
  Predictable system interconnects through accurate early wire characterization. 287-290
  
• Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande:
  Multiple clock domain synchronization for network on chip architectures. 291-294
  
• Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
  Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity. 295-298
  
• Kang-Chuan Chang, Jun-Wei Lin, Tzi-Dar Chiueh:
  Design of a downlink baseband receiver for IEEE 802.16E OFDMA mode in high mobility. 301-304
  
• Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee:
  An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. 305-308
  
• Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan:
  A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications. 309-312
  
• Zhuo Zou, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng:
  Baseband design for passive semi-UWB wireless sensor and identification systems. 313-316
  

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