SoCC 2011: Taipei, Taiwan

Special Section S1 - Digital Microfluidic Biochips

• Krishnendu Chakrabarty:
  Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore. 5
  
• Paul Pop, Elena Maftei, Jan Madsen:
  Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips. 6-11
  
• Tsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho:
  Recent research and emerging challenges in design and optimization for digital microfluidic biochips. 12-17
  

Section T1 - Embedded Tutorial

• Virendra Singh, Masahiro Fujita:
  Tutorial: "Post silicon debug of SOC designs". 18
  

Section A1 - Green Circuits I

• Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang:
  An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. 19-23
  
• Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
  A gate sizing method for glitch power reduction. 24-29
  
• Na Gong, Geng Tang, Jinhui Wang, Ramalingam Sridhar:
  Novel adaptive keeper LBL technique for low power and high performance register files. 30-35
  
• Xiaoyan Jia, Gerhard Fettweis:
  Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system. 36-41
  
• Yi-Ming Wang, Jen-Tsung Yu, Yuandi Surya, Chung-Hsun Huang:
  A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit. 42-47
  
• Ping-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee:
  A low-power all-digital phase modulator pair for LINC transmitters. 48-51
  
• Shouxian Mou, Kaixue Ma, Kiat Seng Yeo, Nagarajan Mahalingam, Bharatha Kumar Thangarasu:
  A low power wide tuning range VCO with coupled LC tanks. 52-56
  
• Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato:
  A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. 57-62
  

Section B1 - Analog & Biomedical Circuits I

• Godi Fischer, H. Thomas Rossby:
  A silicon core for an acoustic archival tag. 63-69
  
• Po-Yu Kuo, Siwat Saibua, Dian Zhou:
  A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. 70-75
  
• Abhisek Dey, Tarun Kanti Bhattacharyya:
  Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDAC. 76-80
  

Section B2 - EDA and Design Tools

• Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen:
  Simultaneous escape routing based on routability-driven net ordering. 81-86
  
• Supriyo Maji, Pradip Mandal:
  A CAD methodology for automatic topology selection & sizing. 87-92
  
• Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen:
  System power analysis with DVFS on ESL virtual platform. 93-98
  
• Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans:
  A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. 99-104
  

Section P1 - Poster Session & Reception

• Shin-Liang Deng, Chun-Yi Li, Robert Rieger:
  Double-differential recording and AGC using amplifier ASIC. 105-108
  
• Syed R. Naqvi, Ilker Deligoz, Sayfe Kiaei, Bertan Bakkaloglu:
  Dynamic calibration of feedback DAC non-linearity for a 4^th order CT sigma delta for digital hearing aids. 109-113
  
• Harry Tai, Peter Noel, Tad A. Kwasniewski:
  A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system. 114-117
  
• Rajesh Thirugnanam, Dong Sam Ha:
  Feasibility study for communication over Power Distribution Networks of microprocessors. 118-121
  
• Po-Tsang Huang, Yung Chang, Wei Hwang:
  On-demand memory sub-system for multi-core SoCs. 122-127
  
• Kaijian Shi, David Tester:
  Well tapping methodologies in power-gating design. 128-131
  
• Shui-An Wen, Huang-Lun Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng:
  Power-aware design technique for PAC Duo based embedded system. 132-135
  
• Janna Mezhibovsky, Adam Teman, Alexander Fish:
  Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM. 136-141
  
• Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto:
  Ultra low power QC-LDPC decoder with high parallelism. 142-145
  
• An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting:
  A SAR ADC BIST for simplified linearity test. 146-149
  
• Meganathan Deivasigamani, Shaghayeghsadat Tabatabaei, Naveed Mustafa, Hamza Ijaz, Haris Bin Aslam, Shaoteng Liu, Axel Jantsch:
  Concept and design of exhaustive-parallel search algorithm for Network-on-Chip. 150-155
  
• Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang:
  TSV sharing through multiplexing for TSV count minimization in high-level synthesis. 156-159
  
• Maher Rashed, Mohamed A. Abd El-Ghany, Mohammed Ismail:
  Power characteristics of Asynchronous Networks-on-Chip. 160-165
  
• Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
  Design of complex circuits using the Via-Configurable transistor array regular layout fabric. 166-169
  
• Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey:
  Yield-award placement optimization for Switched-Capacitor analog integrated circuits. 170-173
  
• Mu-Tien Chang, Bruce Jacob:
  An analytical model to estimate PCM failure probability due to process variations. 174-177
  

Section PL2 - Plenary Session II

• Gideon D. Intrater:
  Plenary: Boosting performance efficiency in multiprocessor systems through multi-threading. 178
  

Section A3 - Embedded and Multicore Systems

• Amayika Panda, Annie Avakian, Ranga Vemuri:
  Configurable workload generators for multicore architectures. 179-184
  
• Samarth Kaushik, Amit Kumar Singh, Thambipillai Srikanthan:
  Computation and communication aware run-time mapping for NoC-based MPSoC platforms. 185-190
  
• Azeez Sanusi, Magdy A. Bayoumi:
  De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips. 191-196
  
• Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
  A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. 197-200
  

Section B3 - Verification and Test

• Yi-Li Lin, Alvin W. Y. Su:
  Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform. 201-206
  
• Liucheng Guo, Jiangfang Yi, Liang Zhang, Xiaoyin Wang, Dong Tong:
  CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors. 207-212
  
• Chang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin:
  High reliability built-in self-detection and self-correction design for DCT/IDCT application. 213-218
  
• Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin:
  A register-transfer level testability analyzer. 219-224
  

Section A4 - Technology and Variation

• Joan Mauricio, Francesc Moll, Josep Altet:
  Monitor strategies for variability reduction considering correlation between power and timing variability. 225-230
  
• Rami F. Salem, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, Haitham Eissa, Mohamed Dessouky, David Nairn, Mohab H. Anis:
  A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow. 231-236
  
• Yuichiro Yamaji, Minoru Watanabe:
  A 144-configuration context MEMS optically reconfigurable gate array. 237-241
  

Section B4 - Communication Circuits

• Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang:
  VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. 242-246
  
• Yi-Pei Su, Wei-Yi Hu, Jia-Wei Lin, Yun-Chung Chen, Sakir Sezer, Sao-Jie Chen:
  Low power Gm-boosted differential Colpitts VCO. 247-250
  
• Behzad Mesgarzadeh, Iman Esmaeil Zadeh, Atila Alvandpour:
  A multi-segment clocking scheme to reduce on-chip EMI. 251-255
  

Luncheon Speaker

• Laung-Terng Wang:
  Luncheon Speaker: "Introduction to SoC testing". 256-257
  

Special session S2 - Software Defined Radio

• Tzi-Dar Chiueh:
  Baseband signal processing in SDR. 258
  
• Ruolin Zhou, Xue Li, Jian Zhang, Zhiqiang Wu:
  Software defined radio based frequency domain chaotic cognitive radio. 259-264
  
• Jen-Yuan Hsu, Chien-Yu Kao, Ping-Heng Kuo, Pangan Ting:
  Configurable baseband designs and implementations of WiMAX/LTE dual systems based on multi-core DSP. 265-271
  

Section T2 - Embedded Tutorial

• Jacob A. Abraham:
  Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)". 272
  

Section A5 - Network on Chip (Noc)

• Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu:
  Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon. 273-277
  
• Falko Guderian, Erik Fischer, Markus Winter, Gerhard Fettweis:
  Fair rate packet arbitration in Network-on-Chip. 278-283
  
• Chih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu Wu:
  Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems. 284-289
  
• Yi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu:
  TSV-based 3D-IC placement for timing optimization. 290-295
  
• Yi-Xue Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li:
  Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits. 296-301
  
• Ye Lu, John V. McCanny, Sakir Sezer:
  Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. 302-307
  
• Chih-Chyau Yang, Nien-Hsiang Chang, Shih-Lun Chen, Wei-De Chien, Chi-Shi Chen, Chien-Ming Wu, Chun-Ming Huang:
  A novel methodology for Multi-Project System-on-a-Chip. 308-311
  

Section B5 - Architecture & Multimedia Systems

• Siegfried Brandstätter, Mario Huemer:
  VFSMC - a core for cycle accurate multithreaded processing in hard real-time Systems-on-Chip. 312-317
  
• Yuan Cao, Amine Bermak:
  An analog gamma correction method for high dynamic range applications. 318-322
  
• Na Gong, Geng Tang, Jinhui Wang, Ramalingam Sridhar:
  Low power tri-state register files design for modern out-of-order processors. 323-328
  

Section B6 - Reconfigurable Systems

• Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan:
  Instruction set customization for area-constrained FPGA designs. 329-334
  
• Alexander Thomas, Michael Rückauer, Jürgen Becker:
  HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture. 335-340
  
• Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan:
  Compiler-assisted technique for rapid performance estimation of FPGA-based processors. 341-346
  
• Thianantha Arumugam, Sakir Sezer, Dwayne Burns, Vishalini Vasu:
  High performance multi-engine regular expression processing. 347-352
  

Section T3 - Embedded Tutorial

• Jri Lee:
  Tutorial: "Design of high-speed wireline transceivers". 353
  

Section A7 - Green Circuits II

• Yan Zhao, Nianxiong Tan, Kun Yang, Shupeng Zhong, Changyou Men:
  A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode. 354-358
  
• Na Gong, Jinhui Wang, Ramalingam Sridhar:
  PVT variations aware optimal sleep vector determination of dual VT domino OR circuits. 359-364
  
• Hailong Jiao, Volkan Kursun:
  Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits. 365-370
  

Section B7 - Analog & Biomedical Circuits II

• Tzu-Chun Shih, Tsan-Wen Chen, Wei-Hao Sung, Ping-Yuan Tsai, Chen-Yi Lee:
  An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications. 371-375
  
• Kai-Wen Yao, Cihun-Siyong Alex Gong, Shan-Ci Yang, Muh-Tian Shiue:
  Design of a neural recording amplifier with tunable pseudo resistors. 376-379
  
• Rajaram Mohan Roy Koppula, Sakkarapani Balagopal, Vishal Saxena:
  Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs. 380-385
  

Section A8 - Invited Talks from IBM

• Jeffrey L. Burns:
  Technology trends and implications on SoC design. 386
  
• Stefanie Chiras:
  The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems development. 387
  
• Jeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy:
  Floorplanning challenges in early chip planning. 388-393
  

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