Timing Issues In The Specification And Synthesis Of Digital Systems 2002: Monterey, CA, USA

@proceedings{DBLP:conf/tau/2002,
  editor    = {David P. LaPotin and
               Charles J. Alpert and
               John Lillis},
  title     = {Proceedings of the 8th ACM/IEEE International Workshop on Timing
               Issues in the Specification and Synthesis of Digital Systems,
               Monterey, California, USA, December 2-3, 2002},
  booktitle = {Timing Issues in the Specification and Synthesis of Digital Systems},
  publisher = {ACM},
  year      = {2002},
  isbn      = {1-58113-526-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Process variation

• Louis Scheffer:
  Explicit computation of performance as a function of process variation. 1-8
  
• Joni Dambre, Dirk Stroobandt, Jan Van Campenhout:
  A probabilistic approach to clock cycle prediction. 9-15
  
• Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
  Statistical timing analysis using bounds and selective enumeration. 16-21
  
• Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal:
  Worst case clock skew under power supply variations. 22-28
  
• Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
  Statistical timing analysis using bounds and selective enumeration. 29-36
  

New directions in timing analysis

• Kurt Keutzer, Michael Orshansky:
  From blind certainty to informed uncertainty. 37-41
  
• Avi Efrati, Moshe Kleyner:
  Timing analysis challenges for high speed CPUs at 90nm and below. 42
  

Topics in timing

• Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer:
  Minimum-power retiming for dual-supply CMOS circuits. 43-49
  
• Ali Dasdan:
  Efficient algorithms for debugging timing constraint violations. 50-56
  
• Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
  PERI: a technique for extending delay and slew metrics to ramp inputs. 57-62
  
• Kanak Agarwal, Dennis Sylvester, David Blaauw:
  A library compatible driving point model for on-chip RLC interconnects. 63-69
  
• Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang:
  Aggressive crunching of extracted RC netlists. 70-77
  

Issues in crosstalk

• Hai Zhou:
  Clock schedule verification with crosstalk. 78-83
  
• Bhavana Thudi, David Blaauw:
  Efficient switching window computation for cross-talk noise. 84-91
  
• Jun Chen, Lei He:
  Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. 92-97
  
• Himanshu Kaul, Dennis Sylvester, David Blaauw:
  Active shielding of RLC global interconnects. 98-104
  

Emerging technologies and trends

• Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, K. O. Kenneth:
  Wireless interconnects for clock distribution. 105-108
  

Design for manufacturability

• Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu:
  Test structures for delay variability. 109
  

Optimization

• Baris Taskin, Ivan S. Kourtev:
  Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. 111-118
  
• Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili:
  Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. 119-125
  
• Paul I. Pénzes, Mika Nyström, Alain J. Martin:
  Transistor sizing of energy-delay--efficient circuits. 126-133
  
• Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga:
  The statistical longest path problem and its application to delay analysis of logical circuits. 134-139
  
• Sangyun Kim, Sunan Tugsinavisut, Peter A. Beerel:
  Reducing probabilistic timed petri nets for asynchronous architectural analysis. 140-147