VLSI 1993:
Grenoble,
France
Kakayuki Yanagawa, Peter A. Ivey (Eds.):
VLSI 93, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September, 1993.
IFIP Transactions A-42 North-Holland 1994, ISBN 0-444-89911-1 
@proceedings{DBLP:conf/vlsi/1993,
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {VLSI 93, Proceedings of the IFIP TC10/WG 10.5 International Conference
on Very Large Scale Integration, Grenoble, France, 7-10 September,
1993},
booktitle = {VLSI},
publisher = {North-Holland},
series = {IFIP Transactions},
volume = {A-42},
year = {1994},
isbn = {0-444-89911-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote
Layout Synthesis
Special Purpose Architectures
Design for Testability
- Michael Gössel, Egor S. Sogomonyan:
Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design.
103-111
- Albrecht P. Stroele:
Partitioning and hierarchical description of self-testable designs.
113-122
- Régis Leveugle:
Test of single fault tolerant controllers in VLSI circuits.
123-132
- W. A. J. Waller, S. M. Aziz:
A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic.
133-142
Image Processing
- D. Poussart:
Opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensors.
145-150
- J. Schönfeld, Peter Pirsch:
Single board image processing unit for vehicle guidance.
151-160
- Jaap Smit, Mark J. Bentum, Martin M. Samsom:
Implementation of the volume rendering algorithm using a low-power design-style.
161-168
- D. Jacquet, Gabriele Saucier:
Design of a dedicated neural network on silicon: application to optical character recognition.
169-178
High Performance Processors
- Mike Muller:
ARM6: Processor design for high performance at low power.
181-189
- Albert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens:
A new method for retiming multi-functional processing units.
191-200
- Ganesh Gopalakrishnan, Venkatesh Akella:
A transformational approach to asynchronous high-level synthesis.
201-210
- Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods:
A micropipelined ARM.
211-220
- F. Poirier, Jean-Claude Heudin, M. Belleville, C. Jaffard:
A high performance RISC microprocessor.
221-228
Low Level Models
Multichip Modules
Routing
Simulation
Copyright © Tue Nov 10 00:21:37 2009
by Michael Ley (ley@uni-trier.de)
