VLSI-SoC 2007: Atlanta, GA, USA

• Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri:
  Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. 1-6
  
• C. M. Markan, Priti Gupta:
  Neuromorphic building blocks for adaptable cortical feature maps. 7-12
  
• Sheng-Yu Peng, Paul E. Hasler, David V. Anderson:
  An analog programmable multi-dimensional radial basis function based classifier. 13-18
  
• Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio:
  ReCPU: A parallel and pipelined architecture for regular expression matching. 19-24
  
• Osnat Keren, Ilya Levin, Radomir S. Stankovic:
  Use of gray decoding for implementation of symmetric functions. 25-30
  
• Jorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira:
  Parametric structure-preserving model order reduction. 31-36
  
• Hua Tang:
  Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators. 37-41
  
• Sameer Sharma, L. G. Johnson:
  First order quasi-static SOI MOSFET channel capacitance model. 42-47
  
• Almitra Pradhan, Ranga Vemuri:
  Regression based circuit matrix models for accurate performance estimation of analog circuits. 48-53
  
• Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris:
  A software-supported methodology for designing high-performance 3D FPGA architectures. 54-59
  
• Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau:
  Estimating design time for system circuits. 60-65
  
• Antonio Carlos Schneider Beck, Luigi Carro:
  Transparent acceleration of data dependent instructions for general purpose processors. 66-71
  
• Dimitrios N. Serpanos, Wayne Wolf:
  VLSI models of network-on-chip interconnect. 72-77
  
• Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Gilson I. Wirth, Ralf Brederlow, Christian Pacha:
  Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. 78-83
  
• Yikui Dong, Steve Howard, Freeman Zhong, Scott Lowrie, Ken Paradis, Jan Kolnik, Jeff Burleson:
  AC-coupling strategy for high-speed transceivers of 10Gbps and beyond. 84-87
  
• Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
  SWORD: A SAT like prover using word level information. 88-93
  
• Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis:
  Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. 94-98
  
• Vyas Krishnan, Srinivas Katkoori:
  Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. 99-104
  
• Chih-Wen Lu, Yen-Chih Shen, Meng-Lieh Sheu:
  A high-driving class-AB buffer amplifier with a new pseudo source follower. 105-109
  
• Julien Goulier, Eric André, Marc Renaudin:
  A new analytical approach of the impact of jitter on continuous time delta sigma converters. 110-115
  
• Adriel Ziesemer, Cristiano Lazzari:
  Transistor level automatic layout generator for non-complementary CMOS cells. 116-121
  
• Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi:
  Computing and design for software and silicon manufacturing. 122-127
  
• Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto:
  An adaptive genetic algorithm for dynamically reconfigurable modules allocation. 128-133
  
• Jürgen Becker, Adam Donlin, Michael Hübner:
  New tool support and architectures in adaptive reconfigurable computing. 134-139
  
• Aline Mello, Ney Laert Vilar Calazans:
  Rate-based scheduling policy for QoS flows in networks on chip. 140-145
  
• Nan Jiang, David Harris:
  Parallelized radix-2 scalable Montgomery multiplier. 146-150
  
• Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour:
  An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. 151-156
  
• Pranav Vaidya, Jaehwan John Lee:
  Simulation of hybrid computer architectures: simulators, methodologies and recommendations. 157-162
  
• Satnam Singh:
  New parallel programming techniques for hardware design. 163-167
  
• Shiv Balakrishnan, Chris Eddington:
  Efficient DSP algorithm development for FPGA and ASIC technologies. 168-171
  
• Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
  Incremental placement for structured ASICs using the transportation problem. 172-177
  
• Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
  Test data compression and TAM design. 178-183
  
• Krishna Santhanam, Kenneth S. Stevens:
  Dynamic gates with hysteresis and configurable noise tolerance. 184-189
  
• Jaemoon Kim, Sangkwon Na, Chong-Min Kyung:
  A low-power deblocking filter architecture for H.264 advanced video coding. 190-193
  
• Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
  The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. 194-199
  
• Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin:
  An efficient H.264 intra frame coder system design. 200-205
  
• Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro:
  Qualification of behavioral level design validation for AMS & RF SoCs. 206-211
  
• Jean Carlo Hamerski, Everton Reckziegel, Fernanda Lima Kastensmidt:
  Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack. 212-217
  
• Youssef Serrestou, Vincent Beroulle, Chantal Robach:
  Impact of hardware emulation on the verification quality improvement. 218-223
  
• Jungsoo Kim, Kyungsu Kang, Heejun Shim, Woong Hwangbo, Chong-Min Kyung:
  Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model. 224-229
  
• Parth Malani, Prakash Mukre, Qinru Qiu:
  Power optimization for conditional task graphs in DVS enabled multiprocessor systems. 230-235
  
• Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci:
  A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes. 236-241
  
• Run Chen, Liyuan Liu, Dongmei Li, Zhihua Wang:
  Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 mum CMO S. 242-247
  
• YuQing Yang, Terry Sculley, Jacob Abraham:
  A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD. 248-251
  
• M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas:
  A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. 252-257
  
• Basab Datta, Wayne P. Burleson:
  Low power on-chip thermal sensors based on wires. 258-263
  
• Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt:
  A low-power CAM using a 12-transistor design cell. 264-269
  
• Alin Razafindraibe, Michel Robert, Philippe Maurine:
  Improvement of dual rail logic as a countermeasure against DPA. 270-275
  
• César A. M. Marcon, Sergio Johann Filho, Fabiano Hessel:
  A VHDL based approach for fast and accurate energy consumption estimations. 276-279
  
• Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar:
  Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis. 280-283
  
• Brian Cody, Justin Madigan, Spencer MacDonald, Kenneth W. Hsu:
  High speed SOC design for blowfish cryptographic algorithm. 284-287
  
• Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris:
  Implementing cellular automata modeled applications on network-on-chip platforms. 288-291
  
• Rishi Bhooshan, Bindu P. Rao:
  Optimum IR drop models for estimation of metal resource requirements for power distribution network. 292-295
  
• Eduardo Wenzel Brião, Daniel Barcelos, Fabio Wronski, Flávio Rech Wagner:
  Impact of task migration in NoC-based MPSoCs for soft real-time applications. 296-299
  
• José Carlos S. Palma, César A. M. Marcon, Fabiano Hessel, Eduardo A. Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Eduardo Reif, Carolina Metzler:
  A Flexible Design Flow for a Low Power RFID Tag. 300-303
  
• Sujan Pandey, Christian Genz, Rolf Drechsler:
  Co-synthesis of custom on-chip bus and memory for MPSoC architectures. 304-307
  
• Vagner S. Rosa, Altamiro Amadeu Susin, Sergio Bampi:
  An HDTV H.264 deblocking filter in FPGA with RGB video output. 308-311
  
• Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis:
  Efficient timing closure with a transistor level design flow. 312-315
  
• J. Luis Tecpanecatl-Xihuitl, Ruth Aguilar-Ponce, Magdy Bayoumi:
  Hybrid multiplierless FIR filter architecture based on NEDA. 316-319
  
• Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay:
  A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. 320-323
  

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