VTS 1995:
Princeton,
NJ,
USA
13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA.
IEEE Computer Society 1995 BibTeX
@proceedings{DBLP:conf/vts/1995,
title = {13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995,
Princeton, New Jersey, USA},
booktitle = {VTS},
publisher = {IEEE Computer Society},
year = {1995},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Advanced Test Pattern Generation Methods
- David E. Long, Mahesh A. Iyer, Miron Abramovici:
Identifying sequentially untestable faults using illegal states.
4-11
Electronic Edition (link) BibTeX
- Srimat T. Chakradhar, Steven G. Rothweiler:
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives.
12-19
Electronic Edition (link) BibTeX
- Mark C. Hansen, John P. Hayes:
High-level test generation using physically-induced faults.
20-28
Electronic Edition (link) BibTeX
- Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva:
A portable ATPG tool for parallel and distributed systems.
29-34
Electronic Edition (link) BibTeX
- Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis:
Testing combinational iterative logic arrays for realistic faults.
35-41
Electronic Edition (link) BibTeX
Mixed-Signal Circuit Test
- Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham:
Verification of transient response of linear analog circuits.
42-47
Electronic Edition (link) BibTeX
- Diego Vázquez, Adoración Rueda, José L. Huertas:
A solution for the on-line test of analog ladder filters.
48-53
Electronic Edition (link) BibTeX
- Khaled Saab, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski:
Frequency-based BIST for analog circuit testin.
54-59
Electronic Edition (link) BibTeX
- Stephen K. Sunter:
A low cost 100 MHz analog test bus.
60-65
Electronic Edition (link) BibTeX
- Lahouari Sebaa, Norm Gardner, Robert Neidorff, Rich Valley:
Self-test in a VCM driver chip.
66-73
Electronic Edition (link) BibTeX
Defect Coverage and Test Quality
- Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams:
On the decline of testing efficiency as fault coverage approaches 100%.
74-83
Electronic Edition (link) BibTeX
- Peter C. Maxwell:
The use of IDDQ testing in low stuck-at coverage situations.
84-88
Electronic Edition (link) BibTeX
- Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel:
Cyclic stress tests for full scan circuits.
89-94
Electronic Edition (link) BibTeX
- J. A. Segura, M. Roca, D. Mateo, A. Rubio:
An approach to dynamic power consumption current testing of CMOS ICs.
95-100
Electronic Edition (link) BibTeX
- J. Arguelles, M. J. Lopez, J. Blanco, M. Martínez, S. Bracho:
Iddt testing of continuous-time filters.
101-107
Electronic Edition (link) BibTeX
Advanced BIST Approaches
Synthesis for Testability
Fault Modeling
Fault Simulation I
Fault Diagnosis
Design for Testability
Iddq Testing
- Marcello Dalpasso, Michele Favalli, Piero Olivo:
Test pattern generation for I/sub DDQ/: increasing test quality.
304-309
Electronic Edition (link) BibTeX
- Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara:
Compact test generation for bridging faults under I/sub DDQ/ testing.
310-316
Electronic Edition (link) BibTeX
- Udo Mahlstedt, Jürgen Alt, Matthias Heinitz:
CURRENT: a test generation system for I/sub DDQ/ testing.
317-323
Electronic Edition (link) BibTeX
- Josep Rius, Joan Figueras:
Detecting I/sub DDQ/ defective CMOS circuits by depowering.
324-329
Electronic Edition (link) BibTeX
- Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira:
Test preparation for high coverage of physical defects in CMOS digital ICs.
330-337
Electronic Edition (link) BibTeX
Automatic Test Pattern Generation
- Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus:
Improving topological ATPG with symbolic techniques.
338-343
Electronic Edition (link) BibTeX
- Tomoo Inoue, Hironori Maeda, Hideo Fujiwara:
A scheduling problem in test generation.
344-349
Electronic Edition (link) BibTeX
- Andrej Zemva, Franc Brglez:
Detectable perturbations: a paradigm for technology-specific multi-fault test generation.
350-357
Electronic Edition (link) BibTeX
- M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor:
Compact test sets for industrial circuits.
358-366
Electronic Edition (link) BibTeX
- Bapiraju Vinnakota, Nicholas J. Stessman:
Reducing test application time in scan design schemes.
367-373
Electronic Edition (link) BibTeX
Delay Fault Testing
Test Pattern Generation for BIST
Self-Checking Systems I
- Samvel K. Shoukourian, Armen G. Kostanian, Valery A. Margarian, Ayman A. Ashour:
An approach for system tests design and its application.
448-453
Electronic Edition (link) BibTeX
- Alessandro Bogliolo, Maurizio Damiani:
Synthesis of combinational circuits with special fault-handling capabilitie.
454-459
Electronic Edition (link) BibTeX
- B. Hamdi, H. Bederr, Michael Nicolaidis:
A tool for automatic generation of self-checking data paths.
460-466
Electronic Edition (link) BibTeX
- Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen:
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers.
467-471
Electronic Edition (link) BibTeX
- Walter W. Weber, Adit D. Singh:
An experimental evaluation of the differential BICS for I/sub DDQ/ testing.
472-485
Electronic Edition (link) BibTeX
Best Paper - 1994
Copyright © Wed Aug 20 20:15:04 2008
by Michael Ley (ley@uni-trier.de)
