VTS 1998: Princeton, NJ, USA

Core and System on Chip Test

• Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin G. Stawiasz:
  Designing a Testable System on a Chip. 2-7
  
• Debashis Bhattacharya:
  Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. 8-14
  
• Mehrdad Nourani, Christos A. Papachristou:
  Parallelism in Structural Fault Testing of Embedded Cores. 15-21
  

Testing Deep Submicron Circuits

• Ovidio V. Maiuri, Will R. Moore:
  Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm. 22-27
  
• Petra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, T. W. Williams:
  Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores. 28-33
  
• Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham:
  Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. 34-41
  

Diagnosis and Validation

• Jun Zhao, Fred J. Meyer, Fabrizio Lombardi:
  Fault Detection and Diagnosis of Interconnects of Random Access Memories. 42-47
  
• Kazuki Shigeta, Toshio Ishiyama:
  A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis. 48-53
  
• Pradip Bose:
  Performance Test Case Generation for Microprocessors. 54-61
  

BIST 1

• Masahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi:
  COMPACT: A Hybrid Method for Compressing Test Data. 62-69
  
• Bahram Pouya, Nur A. Touba:
  Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. 70-77
  
• Albrecht P. Stroele:
  Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. 78-85
  

Scan & Boundary Scan

• Amitava Majumdar, Michio Komoda, Tim Ayres:
  Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. 86-91
  
• T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos:
  Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. 92-97
  
• Kamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III:
  Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips. 98-105
  

IDDQ and VLV Test

• Víctor H. Champac, José Castillejos, Joan Figueras:
  IDDQ Testing of Opens in CMOS SRAMs. 106-111
  
• Tsuyoshi Shinogi, Terumine Hayashi:
  A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. 112-117
  
• Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey:
  Experimental Results for IDDQ and VLV Testing. 118-125
  

Analog Test

• Michael W. Tian, C.-J. Richard Shi:
  Nonlinear Analog DC Fault Simulation by One-Step Relaxation. 126-131
  
• Pramodchandran N. Variyam, Abhijit Chatterjee:
  Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements. 132-137
  
• Madhu K. Iyer, Michael L. Bushnell:
  Effect of Noise on Analog Circuit Testing. 138-144
  
• Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi:
  Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. 145-151
  

Sequential Test and Redundancy Removal

• Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
  Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. 152-157
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On Synchronizing Sequences and Test Sequence Partitioning. 158-167
  
• Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
  On Removing Redundant Faults in Synchronous Sequential Circuits. 168-175
  
• Hiroyuki Yotsuyanagi, Kozo Kinoshita:
  Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. 176-183
  

Embedded Tutorial 1

• Pinaki Mazumder:
  Analysis of Failures in Deep Submicron SRAM Cells. 184-187
  

Delay Fault Test

• Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro:
  Efficient Path Selection for Delay Testing Based on Partial Path Evaluation. 188-193
  
• Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell:
  On Delay-Untestable Paths and Stuck-Fault Redundancy. 194-199
  
• Uwe Sparmann, Lars Köller:
  Improving Path Delay Fault Testability by Path Removal. 200-209
  

BIST 2

• Ganapathy Parthasarathy, Michael L. Bushnell:
  Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. 210-217
  
• Janusz Rajski, Jerzy Tyszer:
  Design of Phase Shifters for BIST Applications. 218-224
  
• Jacob Savir:
  Distributed Generation of Weighted Random Patterns. 225-233
  

Testing High-Speed Circuits

• David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz:
  High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. 234-238
  
• Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska, Fartoumi M. Hossein, Patrick Vincent:
  Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing. 239-244
  
• Ralph Mason, Shing Ma:
  Mixed Signal DFT at GHz Frequencies. 245-253
  

Validation/Verification

• Dinos Moundanos, Jacob A. Abraham:
  Using Verification Technology for Validation Coverage Analysis and Test Generation. 254-259
  
• Li-C. Wang, Magdy S. Abadir, Jing Zeng:
  On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. 260-265
  
• Rongchang Yan, Bruce C. Kim:
  A Novel Routing Algorithm for MCM Substrate Verification Using Single-Ended Prob. 266-273
  

Defect Level Test

• Douglas Williams, F. Joel Ferguson, Tracy Larrabee:
  A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. 274-282
  
• Fernando M. Gonçalves, João Paulo Teixeira:
  Sampling Techniques of Non-Equally Probable Faults in VLSI System. 283-288
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. 289-295
  

Concurrent Checking & Fault Tolerance

• Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich:
  Fast Self-Recovering Controllers. 296-302
  
• Charles E. Stroud, Joe K. Tannehill Jr.:
  Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits. 303-308
  
• Debaleena Das, Nur A. Touba:
  Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. 309-317
  

Panel 1

• José M. Miranda, Scott Davidson, Peter Dziel, Saman Adham, Steve Millman:
  Test Reuse at System Level. 318-319
  

Panel and Embedded Tutorial 2

• Jean-Michel Karam, Marcelo Lubaszewski, S. Blanton, Andrew Richardson:
  Testing MEMS. 320-321
  

Embedded Tutorial 3

• Sandip Gupta, Craig Gleason:
  Validation and Test Problems for Cross Talk Noise. 322-323
  

Scan Techniques

• Egor S. Sogomonyan, Adit D. Singh, Michael Gössel:
  A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. 324-331
  
• Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe:
  Low Cost Partial Scan Design: A High Level Synthesis Approach. 332-340
  
• Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
  Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. 341-347
  

On-Line Testing

• Xrysovalantis Kavousianos, Dimitris Nikolos:
  Novel Single and Double Output TSC Berger Code Checkers. 348-353
  
• Markus Seuring, Michael Gössel, Egor S. Sogomonyan:
  A Structural Approach for Space Compaction for Concurrent Checking and BIST. 354-361
  
• Arsen Kuchukyan:
  Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under Check. 362-369
  

Analog/Mixed Signal Test and DFT

• Florence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin:
  Design-For-Testability for Switched-Current Circuits. 370-375
  
• A. Lechner, Andrew Richardson, B. Hermes, Michael J. Ohletz:
  A Design for Testability Study on a High Performance Automatic Gain Control Circuit. 376-385
  
• R. de Vries, Augustus J. E. M. Janssen:
  Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling. 386-393
  

Memory Test

• Sultan M. Al-Harbi, Sandeep K. Gupta:
  A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. 394-400
  
• A. J. van de Goor, Said Hamdioui:
  Fault Models and Tests for Two-Port Memories. 401-410
  
• Piotr R. Sidorowicz, Janusz A. Brzozowski:
  An Approach to Modeling and Testing Memories and Its Application to CAMs. 411-417
  

BIST 3

• Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray:
  Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. 418-423
  
• Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda:
  On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. 424-429
  
• Bruce F. Cockburn, Albert L.-C. Kwong:
  Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators. 430-439
  

New ATPG Techniques

• Dimitrios Karayiannis, Spyros Tragoudas:
  A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. 440-445
  
• Ilker Hamzaoglu, Janak H. Patel:
  New Techniques for Deterministic Test Pattern Generation. 446-452
  
• Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
  A Test Pattern Generation Methodology for Low-Power Consumption. 453-459
  

Panel 3

• Peter C. Maxwell, Steve Baird, Wayne M. Needham, Al Crouch, Phil Nigh:
  Best Methods for At-Speed Testing? 460-461
  

Embedded Tutorial 4

• Jeffrey S. Kasten:
  An Introduction to RF Testing: Device, Method and System. 462-469
  

Panel 4

• Keerthi Heragu:
  Where We Might Stumble with Embedded-System Test. 470