VTS 1999: San Diego, CA, USA

Keynote Address

• Vinod K. Agarwal:
  VTS 1999 Keynote Address Embedded Test OR External Test. 2-7
  

Invited Presentation

• Hugo De Man:
  Design Technology Research and Education for Deep-Submicron Systems of the Next Century. 8-15
  

Testing High-Speed and Dynamic Circuits

• Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar:
  Testing High Speed VLSI Devices Using Slower Testers. 16-21
  
• Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
  Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. 22-27
  
• R. Dean Adams, Edmond S. Cooley:
  The Limits of Digital Testing for Dynamic Circuits. 28-33
  

Core Testing

• Ken Batcher, Christos A. Papachristou:
  Instruction Randomization Self Test For Processor Cores. 34-40
  
• Irith Pomeranz, Yervant Zorian:
  Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. 41-48
  
• Michael Gössel, A. A. Morosov, Egor S. Sogomonyan:
  A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces. 49-57
  

Diagnosis

• Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs:
  Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. 58-63
  
• Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu:
  A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. 64-69
  
• Debashis Nayak, D. M. H. Walker:
  Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. 70-79
  

Techniques for the Very-Deep Submicron

• Michael A. Margolese, F. Joel Ferguson:
  Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. 80-85
  
• Michael Nicolaidis:
  Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies. 86-94
  
• Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
  Test Generation for Ground Bounce in Internal Logic Circuitry. 95-105
  

Advanced Scan Path Techniques

• Josef Schmid, Joachim Knäblein:
  Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs. 106-113
  
• Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba:
  Scan Vector Compression/Decompression Using Statistical Coding. 114-120
  
• Sameer Sharma, Michael S. Hsiao:
  Partial Scan Using Multi-Hop State Reachability Analysis. 121-127
  

IDDQ Testing

• Robert C. Aitken:
  Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage. 128-134
  
• Th. Calin, Lorena Anghel, Michael Nicolaidis:
  Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS. 135-142
  
• Claude Thibeault:
  On the Comparison of IDDQ and IDDQ Testing. 143-151
  

Delay Fault Testing

• Irith Pomeranz, Sudhakar M. Reddy:
  A Flexible Path Selection Procedure for Path Delay Fault Testing. 152-159
  
• Hyungwon Kim, John P. Hayes:
  Delay Fault Testing of Designs with Embedded IP Cores. 160-167
  
• Jayabrata Ghosh-Dastidar, Nur A. Touba:
  Adaptive Techniques for Improving Delay Fault Diagnosis. 168-172
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. 173-181
  

Validation, Verification, and Diagnosis

• Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
  Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. 182-188
  
• Jian Shen, Jacob A. Abraham:
  Verification of Processor Microarchitectures. 189-194
  
• Sreejit Chakravarty, Vinodh Gopal:
  Techniques to Encode and Compress Fault Dictionaries. 195-200
  
• Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
  Implication and Evaluation Techniques for Proving Fault Equivalence. 201-213
  

Mixed Signal Testing

• Pramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee:
  Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation. 214-219
  
• Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng:
  Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. 220-225
  
• Stephen K. Sunter, Naveena Nagi:
  Test Metrics for Analog Parametric Faults. 226-235
  

BIST

• Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer:
  Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. 236-245
  
• Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee:
  An Efficient BIST Method for Small Buffers. 246-251
  
• Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian:
  An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. 252-259
  

ATPG Related Approaches

• Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
  A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. 260-267
  
• Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer:
  REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. 268-274
  
• Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin:
  Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. 275-283
  

Testing MEMS, MCM and Analog Circuits

• Bruce C. Kim, Krishna Marella:
  A Novel Test Methodology for MEMS Magnetic Micromotors. 284-289
  
• Zao Yang, Kwang-Ting Cheng, K. L. Tai:
  A New Bare Die Test Methodology. 290-295
  
• Ramakrishna Voorakaranam, Abhijit Chatterjee:
  Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. 296-303
  

Mixed Signal BIST

• Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis:
  A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits. 304-310
  
• Sassan Tabatabaei, André Ivanov:
  A Current Integrator for BIST of Mixed-Signal ICs. 311-318
  
• Jinyan Zhang, Sam D. Huynh, Mani Soma:
  A Test Point Insertion Algorithm for Mixed-Signal Circuits. 319-325
  

High-Level Test Techniques

• Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
  Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. 326-332
  
• Ronald J. Hayne, Barry W. Johnson:
  Behavioral Fault Modeling in a VHDL Synthesis Environment. 333-340
  
• Silvia Chiusano, Fulvio Corno, Paolo Prinetto:
  RT-level TPG Exploiting High-Level Synthesis Information. 341-353
  

Concurrent Checking

• Xrysovalantis Kavousianos, Dimitris Nikolos:
  Modular TSC Checkers for Bose-Lin and Bose Codes. 354-360
  
• Albrecht P. Stroele, Steffen Tarnick:
  Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. 361-369
  
• Debaleena Das, Nur A. Touba:
  Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. 370-377
  

Memory Test: Moderators

• Jun Zhao, Fred J. Meyer, Fabrizio Lombardi:
  Maximal Diagnosis of Interconnects of Random Access Memories. 378-383
  
• Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
  Error Detecting Refreshment for Embedded DRAMs. 384-390
  
• Kamran Zarrineh, Shambhu J. Upadhyaya:
  A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units. 391-397
  

BIST Related Approaches

• Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
  TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. 398-406
  
• Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
  A Test Vector Inhibiting Technique for Low Energy BIST Design. 407-412
  
• Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud:
  Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access. 413-419
  

Defect Oriented Test

• Eugeni Isern, Miquel Roca, Jaume Segura:
  Analyzing the Need for ATPG Targeting GOS Defects. 420-425
  
• Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita:
  On the Evaluation of Arbitrary Defect Coverage of Test Sets. 426-432
  
• Wanli Jiang, Bapiraju Vinnakota:
  Defect-Oriented Test Scheduling. 433-439
  

On-Line Testing and Fault Tolerance

• Philip P. Shirvani, Edward J. McCluskey:
  PADded Cache: A New Fault-Tolerance Technique for Cache Memories. 440-445
  
• Ismet Bayraktaroglu, Alex Orailoglu:
  Low-Cost On-Line Test for Digital Filters. 446-451
  
• Maurizio Rebaudengo, Matteo Sonza Reorda:
  Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . 452-459
  

DFT and Boundary Scan

• Jingjing Xu, Rahul Kundu, F. Joel Ferguson:
  A Systematic DFT Procedure for Library Cells. 460-466
  
• Debashis Bhattacharya:
  Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. 467-472
  
• Gustavo R. Alves, Jose M. Martins Ferreira:
  From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1. 473-486
  

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