VTS 2003: Napa Valley, CA, USA

21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA. IEEE Computer Society 2003, ISBN 0-7695-1924-5

Plenary Session

Jon Fields:
Keynote Address. 3
Philippe Magarshack:
Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies. 4

New Directions in Scan Test

Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams:
A Reconfigurable Shared Scan-in Architecture. 9-14
Manish Sharma, Janak H. Patel, Jeff Rearick:
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. 15-21
Magdy S. Abadir, Juhong Zhu:
Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. 22-30

Outlier Identification & Current Based Test

Sagar S. Sabade, D. M. H. Walker:
Use of Multiple IDDQ Test Metrics for Outlier Identification. 31-38
Brady Benware, Robert Madge, Cam Lu, W. Robert Daasch:
Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs. 39-46
Thomas J. Vogels:
Effectiveness of I-V Testing in Comparison to IDDq Tests. 47-56

Advances in Built-In Self-Test - I

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
High Speed Ring Generators and Compactors of Test Data. 57-62
Ahmad A. Al-Yamani, Edward J. McCluskey:
Built-In Reseeding for Serial Bist. 63-68
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Bist Reseeding with very few Seeds. 69-76

Analog and Mixed-Signal Test - I

Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Ultra Low Cost Analog BIST Using Spectral Analysis. 77-82
Hak-soo Yu, Sungbae Hwang, Jacob A. Abraham:
DSP-Based Statistical Self Test of On-Chip Converters. 83-88
Soumendu Bhattacharya, Abhijit Chatterjee:
High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost. 89-100

Test Compaction

Peter Wohl, Leendert M. Huisman:
Analysis and Design of Optimal Combinational Compactors. 101-106
Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy:
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. 107-112
Ismet Bayraktaroglu, Alex Orailoglu:
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. 113-120

Testing Buses and On-Chip Interconnect

Kartik Mohanram, Nur A. Touba:
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. 121-127
Érika F. Cota, Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin:
The Impact of NoC Reuse on the Testing of Core-based Systems. 128-133
Mehdi Baradaran Tahoori, Subhasish Mitra:
Automatic Configuration Generation for FPGA Interconnect Testing. 134-144

Test Challenges in Nanometer Technologies

José Pineda de Gyvez, Rosa Rodríguez-Montañés:
Threshold Voltage Mismatch (DeltaVT) Fault Modeling. 145-150
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce Considering Circuit Delay. 151-157
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani:
Testing SoC Interconnects for Signal Integrity Using Boundary Scan. 158-172

Advanced Test Generation and Fault Simulation Techniques

Irith Pomeranz, Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. 173-178
Aiman H. El-Maleh, Khaled Al-Utaibi:
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. 179-185
Nabil M. Abdulrazzaq, Sandeep K. Gupta:
Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. 186-196

Analog and Mixed-Signal Test - 2

Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng:
1149.4 Based On-Line Quiescent State Monitoring Technique. 197-202
Mani Soma, Welela Haileselassie, Jessica Sherrid:
Measurement of Phase and Frequency Variations in Radio-Frequency Signal. 203-208
Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. 209-218

Test Data Compression

Lei Li, Krishnendu Chakrabarty:
Test Data Compression Using Dictionaries with Fixed-Length Indices. 219-224
Kedarnath J. Balakrishnan, Nur A. Touba:
Deterministic Test Vector Decompression in Software Using Linear Operations. 225-231
Erik H. Volkerink, Subhasish Mitra:
Efficient Seed Utilization for Reseeding based Compression. 232-240

Memory Testing

Said Hamdioui, A. J. van de Goor, Mike Rodgers:
Detecting Intra-Word Faults in Word-Oriented Memories. 241-247
Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Test and Diagnosis of Word-Oriented Multiport Memories. 248-253
Sultan M. Al-Harbi, Sandeep K. Gupta:
Generating Complete and Optimal March Tests for Linked Faults in Memories. 254-266

Power Consumption and Test

Xiaoding Chen, Michael S. Hsiao:
Energy-Efficient Logic BIST Based on State Correlation Analysis. 267-272
Dan Zhao, Shambhu J. Upadhyaya:
Power Constrained Test Scheduling with Dynamically Varied TAM. 273-278
Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota:
Development of Energy Consumption Ratio Test. 279-286

Testing Core-Based SoCs

Tomokazu Yoneda, Hideo Fujiwara:
Design for Consecutive Transparency of Cores in System-on-a-Chip. 287-292
Mohsen Nahvi, André Ivanov:
An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores. 293-298
Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar:
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. 299-312

Panel

Kaushik Roy, T. M. Mak, Kwang-Ting Cheng:
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. 313-318

System-Level Test Issues

Erik Larsson, Hideo Fujiwara:
Test Resource Partitioning and Optimization for SOC Designs. 319-324
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang:
SOC Test Scheduling Using Simulated Annealing. 325-330
Man Wah Chiang, Zeljko Zilic:
Layered Approach to Designing System Test Interfaces. 331-338

Diagnosis Techniques

Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou:
Diagnosis of Delay Defects Using Statistical Timing Models. 339-344
Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger:
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. 345-350
Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. 351-358

Advances in Built-In Self-Test - 2

Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama:
BIST-Aided Scan Test - A New Method for Test Cost Reduction. 359-364
Dimitri Kagaris:
Built-In TPG with Designed Phaseshifts. 365-370
Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian:
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. 371-378

Test in the Presence of Bridging Faults

Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges. 379-384
Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Analyzing Crosstalk in the Presence of Weak Bridge Defects. 385-392
Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty:
Efficient Implication - Based Untestable Bridge Fault Identifier. 393-402

Emerging Circuit Technologies: Test Challenges

Hans G. Kerkhoff, Mustafa Acar:
Testable Design and Testing of Micro-Electro-Fluidic Arrays. 403-409
Ketan N. Patel, John P. Hayes, Igor L. Markov:
Fault Testing for Reversible Circuits. 410-416
Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun:
Design for Self-Checking and Self-Timed Datapath. 417-430

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