VTS 2010: Santa Cruz, CA, USA

• Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
  Fast path selection for testing of small delay defects considering path correlations. 3-8
  
• Kyriakos Christou, Maria K. Michael, Stelios Neophytou:
  Identification of critical primitive path delay faults without any path enumeration. 9-14
  
• Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
  Path clustering for adaptive test. 15-20
  
• Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li:
  Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. 21-26
  
• Sandra Irobi, Zaid Al-Ars, Said Hamdioui:
  Bit line coupling memory tests for single-cell fails in SRAMs. 27-32
  
• Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo:
  Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. 33-38
  
• Rubin A. Parekhji:
  Innovative practices session 1C: Innovative practices in RF test. 39
  
• Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji:
  Test time reduction using parallel RF test techniques. 40
  
• Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur:
  Density estimation for analog/RF test problem solving. 41
  
• Abhijit Chatterjee, Friedrich Taenzler:
  Low cost test and tuning of RF circuits and systems. 42
  
• Ke Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor:
  A novel hybrid method for SDD pattern grading and selection. 45-50
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Forming multi-cycle tests for delay faults by concatenating broadside tests. 51-56
  
• Adit D. Singh, Chao Han, Xi Qian:
  An output compression scheme for handling X-states from over-clocked delay tests. 57-62
  
• Fahad Ahmed, Linda Milor:
  Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. 63-68
  
• Young Moon Kim, Tze Wee Chen, Y. Kameda, M. Mizuno, Subhasish Mitra:
  Gate-oxide early-life failure identification using delay shifts. 69-74
  
• Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
  Detecting NBTI induced failures in SRAM core-cells. 75-80
  
• Kwang-Ting Cheng:
  Innovative practices session 2C: Design, fabrication and test of flexible electronics. 81
  
• Kwang-Ting Cheng, Tsung-Ching Huang:
  Design, analysis, and test of low-power and reliable flexible electronics. 82
  
• W. S. Wong:
  Fabrication and testing of large-area flexible electronics for displays and sensor arrays. 83
  
• J. Hu:
  Overview of flexible electronics from ITRI's viewpoint. 84
  
• Sean H. Wu, Sreejit Chakravarty, Li-C. Wang:
  Impact of multiple input switching on delay test under process variation. 87-92
  
• Christian G. Zoellin, Hans-Joachim Wunderlich:
  Low-power test planning for arbitrary at-speed delay-test clock schemes. 93-98
  
• Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja:
  Selecting the most relevant structural Fmax for system Fmax correlation. 99-104
  
• Cihan Tunc, Mehdi Baradaran Tahoori:
  On-the-fly variation tolerant mapping in crossbar nano-architectures. 105-110
  
• Yang Zhao, Krishnendu Chakrabarty:
  Pin-count-aware online testing of digital microfluidic biochips. 111-116
  
• Christopher J. Clark:
  iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages. 117-122
  
• Sarveswara Tammali:
  Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffs. 123
  
• Sarveswara Tammali:
  Industrial practices of test cost reduction: Perspective, current design practices. 124
  
• K. Arnold:
  Adaptive test delivers wide range of sophisticated test solutions. 125
  
• Mokhtar Hirech:
  Test cost and test power conflicts: EDA perspective. 126
  
• Kee Sup Kim:
  Panel 4A: Apprentice - VTS edition: Season 3. 129
  
• Ilia Polian:
  Special session 4B: Panel low-power test and noise-aware test: Foes or friends? 130
  
• Haralampos-G. D. Stratigopoulos:
  Special session 4C: Thesis research poster session. 131
  
• Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji:
  A generic low power scan chain wrapper for designs using scan compression. 135-140
  
• Zhen Chen, Dong Xiang:
  Low-capture-power at-speed testing using partial launch-on-capture test scheme. 141-146
  
• Szu-Pang Mu, Mango Chia-Tso Chao:
  Theoretical analysis for low-power test decompression using test-slice duplication. 147-152
  
• Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li:
  CSER: BISER-based concurrent soft-error resilience. 153-158
  
• Michail Maniatakos, Yiorgos Makris:
  Workload-driven selective hardening of control state elements in modern microprocessors. 159-164
  
• Chien-Chih Yu, John P. Hayes:
  Scalable and accurate estimation of probabilistic behavior in sequential circuits. 165-170
  
• Smriti Gupta:
  Innovative practices session 5C: Post-silicon debug. 171
  
• Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab:
  At-speed scan test with low switching activity. 177-182
  
• Sandeep Bhatia:
  Low power compression architecture. 183-187
  
• Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
  Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. 188-193
  
• Saeed Shamshiri, Kwang-Ting Cheng:
  Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy. 194-199
  
• Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly:
  Evaluating yield and testing impact of sub-wavelength lithography. 200-205
  
• Dongok Kim, Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman:
  Defect diagnosis based on DFM guidelines. 206-211
  
• Karim Arabi:
  Special session 6C: New topic mixed-signal test impact to SoC commercialization. 212
  
• Nitin Yogi, Vishwani D. Agrawal:
  Application of signal and noise theory to digital VLSI testing. 215-220
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On multiple bridging faults. 221-226
  
• Viktor Froese, Rüdiger Ibers, Sybille Hellebrand:
  Reusing NoC-infrastructure for test data compression. 227-231
  
• Yanjing Li, Onur Mutlu, Donald S. Gardner, Subhasish Mitra:
  Concurrent autonomous self-test for uncore components in system-on-chips. 232-237
  
• Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira:
  Low-sensitivity to process variations aging sensor for automotive safety-critical applications. 238-243
  
• Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty:
  Board-level fault diagnosis using Bayesian inference. 244-249
  
• Sandip Ray, Jayanta Bhadra:
  Innovative practices session 7C: Verification and testing challenges in high-level synthesis. 250
  
• Michael Keating:
  The roadblocks to broad adoption of high level synthesis. 251
  
• J. G. Mena, R. Deken, J. E. Coker, M. S. Johnstone, S. R. Ramirez, P. Frey:
  High level synthesis of a Front End filter and DSP engine for analog to digital conversion - a case study. 252
  
• D. Varma, D. Mackay, P. Thiruchelvam:
  Easing the verification bottleneck using high level synthesis. 253-254
  
• Haralampos-G. D. Stratigopoulos:
  Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award. 257
  
• Takahiro Hanyu:
  Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. 258
  
• Arani Sinha:
  Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality? 259
  
• Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai:
  On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. 263-268
  
• Erik Jan Marinissen, Jouke Verbree, Mario H. Konijnenburg:
  A structured and scalable test access architecture for TSV-based 3D stacked ICs. 269-274
  
• Bozena Kaminska, I. L. McWalter:
  Special session 9B: New topic test facilities and infrastructure in Canada. 281
  
• Suriyaprakash Natarajan:
  Innovative practices session 9C: Implications of power delivery network for validation and testing. 282
  
• Eli Chiprout:
  Power delivery dynamics and its impact on silicon validation. 283
  
• Karim Arabi:
  Power noise and its impact on production test and validation of SoC devices. 285
  
• Xuan-Lun Huang, Jiun-Lang Huang:
  An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. 289-294
  
• Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng:
  Calibration-assisted production testing for digitally-calibrated ADCs. 295-300
  
• Nourredine Akkouche, Salvador Mir, Emmanuel Simeu:
  Ordering of analog specification tests based on parametric defect level estimation. 301-306
  
• Zhen Chen, Sharad C. Seth, Dong Xiang:
  A novel hybrid delay testing scheme with low test power, volume, and time. 307-312
  
• Mingjing Chen, Alex Orailoglu:
  VDDmin test optimization for overscreening minimization through adaptive scan chain masking. 313-318
  
• Yiwen Shi, Wan-Chan Hu, Jennifer Dworak:
  Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects. 319-324
  
• Marcello Coppola:
  3D self testing with Spidergon STNoC. 327
  
• Vishwanath Natarajan, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
  A holistic approach to accurate tuning of RF systems for large and small multiparameter perturbations. 331-336
  
• Shyam Kumar Devarakond, Shreyas Sen, Soumendu Bhattacharya, Abhijit Chatterjee:
  Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures. 337-342
  
• Mohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham:
  Multitone digital signal based test for RF receivers. 343-348
  
• Swarup Bhunia, Anand Raghunathan:
  Special session 11B: Hot topic hardware security: Design, test and verification issues. 349
  
• Sreejit Chakravarty:
  Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. 350
  
• Haralampos-G. D. Stratigopoulos:
  Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead. 353
  
• Marcelo Lubaszewski, Érika F. Cota:
  Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip. 354
  
• Kee Sup Kim:
  Panel 12C: Apprentice - VTS edition judging session. 355
  

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